中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.028 seconds)

    METHOD, DEVICE AND SYSTEM FOR PROVIDING ETCHED METALLIZATION STRUCTURES
    5.
    发明申请
    METHOD, DEVICE AND SYSTEM FOR PROVIDING ETCHED METALLIZATION STRUCTURES 有权

    公开(公告)号：US20210289638A1

    公开(公告)日：2021-09-16

    申请号：US17336008

    申请日：2021-06-01

    Applicant: INTEL CORPORATION

    Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

    IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

    Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

    Substrate thermal layer for heat spreader connection
    6.
    发明授权
    Substrate thermal layer for heat spreader connection 有权

    公开(公告)号：US11594463B2

    公开(公告)日：2023-02-28

    申请号：US16158191

    申请日：2018-10-11

    Applicant: Intel Corporation

    Inventor： Nicholas Neal ,  Nicholas Haehn

    IPC: H01L23/00 ,  H01L23/367 ,  H01L23/532

    Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.

    DUMMY DIE IN A RECESSED MOLD STRUCTURE OF A PACKAGED INTEGRATED CIRCUIT DEVICE
    7.
    发明申请
    DUMMY DIE IN A RECESSED MOLD STRUCTURE OF A PACKAGED INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20220102231A1

    公开(公告)日：2022-03-31

    申请号：US17032583

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane

    IPC: H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L25/065

    Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.

    Method, device and system for providing etched metallization structures
    8.
    发明授权
    Method, device and system for providing etched metallization structures 有权

    公开(公告)号：US11116084B2

    公开(公告)日：2021-09-07

    申请号：US16634804

    申请日：2017-09-27

    Applicant: INTEL CORPORATION

    Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

    IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

    Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

Patent Agency Ranking