中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.022 seconds)

    GENERATING AN INTEGRATED CIRCUIT IDENTIFIER
    1.
    发明申请
    GENERATING AN INTEGRATED CIRCUIT IDENTIFIER 审中-公开
    生成集成电路识别器

    公开(公告)号：WO2006032823A3

    公开(公告)日：2006-12-07

    申请号：PCT/FR2005050772

    申请日：2005-09-23

    Applicant: ST MICROELECTRONICS SA ,  MARINET FABRICE

    Inventor： MARINET FABRICE

    IPC: H01L23/544

    CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention concerns the generation of a chip identifier (2) bearing at least one integrated circuit, which consists in providing a cutout of least one conductive path (4) by cutting the chip, the position of the cutting line (3) relative to the chip conditioning the identifier.

    Abstract translation: 本发明涉及产生具有至少一个集成电路的芯片标识符（2），其包括通过切割芯片来提供至少一个导电路径（4）的切口，切割线（3）相对于该切割线 芯片调理标识符。

    Device for the regeneration of a clock signal
    2.
    发明授权
    Device for the regeneration of a clock signal 有权
    用于再生时钟信号的装置

    公开(公告)号：US6362671B2

    公开(公告)日：2002-03-26

    申请号：US77136401

    申请日：2001-01-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： MALHERBE ALEXANDRE ,  MARINET FABRICE ,  POMET ALAIN

    IPC: G06F13/42 ,  G06K19/07 ,  H03K5/01

    CPC classification number: G06K19/07 ,  G06F13/426

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

    4.
    发明专利
    未知

    公开(公告)号：DE60128314T2

    公开(公告)日：2008-01-17

    申请号：DE60128314

    申请日：2001-11-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARINET FABRICE ,  MALHERBE ALEXANDRE

    IPC: H03K3/84 ,  G06F7/58 ,  G06K19/073

    Abstract: Random signal generator comprises an MOS transistor as an electronic noise source. The MOS transistor is operated with a drain source current having a random component and has means for producing a binary random signal from the random drain source current. The current channel is arranged to be curved or S shaped by suitable doping. The invention also relates to an integrated circuit with a binary signal generator based on an MOS transistor. The circuit has suitable connections for connecting to other circuits. An Independent claim is made for a method for generating a random signal from an electronic noise source, in which an MOS transistor with an S or screw shaped channel is used.

    5.
    发明专利
    未知

    公开(公告)号：FR2817361A1

    公开(公告)日：2002-05-31

    申请号：FR0015309

    申请日：2000-11-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： MALHERBE ALEXANDRE ,  MARINET FABRICE

    IPC: G06F7/58 ,  G06K19/073 ,  H03K3/84 ,  G06K19/07

    Abstract: Random signal generator comprises an MOS transistor as an electronic noise source. The MOS transistor is operated with a drain source current having a random component and has means for producing a binary random signal from the random drain source current. The current channel is arranged to be curved or S shaped by suitable doping. The invention also relates to an integrated circuit with a binary signal generator based on an MOS transistor. The circuit has suitable connections for connecting to other circuits. An Independent claim is made for a method for generating a random signal from an electronic noise source, in which an MOS transistor with an S or screw shaped channel is used.

    6.
    发明专利
    未知

    公开(公告)号：FR2804521B1

    公开(公告)日：2002-04-05

    申请号：FR0001061

    申请日：2000-01-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  MALHERBE ALEXANDRE ,  MARINET FABRICE

    IPC: G06F13/42 ,  G06K19/07 ,  G06F1/04 ,  H04L7/00 ,  H03L7/00

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    7.
    发明专利
    未知

    公开(公告)号：DE60128608T2

    公开(公告)日：2008-01-31

    申请号：DE60128608

    申请日：2001-01-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  MALHERBE ALEXANDRE ,  MARINET FABRICE

    IPC: G06F13/42 ,  G06K19/07

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    GENERATION DETERMINISTE D'UN NUMERO D'IDENTIFIANT D'UN CIRCUIT INTEGRE
    8.
    发明专利
    GENERATION DETERMINISTE D'UN NUMERO D'IDENTIFIANT D'UN CIRCUIT INTEGRE 未知

    公开(公告)号：FR2875624A1

    公开(公告)日：2006-03-24

    申请号：FR0452141

    申请日：2004-09-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARINET FABRICE

    IPC: G06K19/073 ,  H01L21/28

    Abstract: L'invention concerne la génération d'un numéro d'identification d'une puce (2) portant au moins un circuit intégré, consistant à provoquer une découpe d'au moins un tronçon conducteur (4) par découpe de la puce parmi plusieurs premiers tronçons conducteurs parallèles entre eux et perpendiculaires à au moins un bord de la puce, les premiers tronçons étant individuellement connectés, par au moins une de leurs extrémités, à la puce et présentant des longueurs différentes les uns des autres, la position du trait de coupe (3) par rapport au bord de la puce conditionnant le numéro d'identification.

    An electronic circuit for detecting a supply potential as having a sufficient value after switching on, for use in integrated circuit devices such as chip cards
    9.
    发明专利
    An electronic circuit for detecting a supply potential as having a sufficient value after switching on, for use in integrated circuit devices such as chip cards 未知

    公开(公告)号：FR2844118A1

    公开(公告)日：2004-03-05

    申请号：FR0210702

    申请日：2002-08-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN ,  MARINET FABRICE

    IPC: H03K17/22

    Abstract: The circuit for detecting a supply potential (VDD,VINT) comprises basically two branches: the first branch with two resistors (R1,R2) and a bipolar transistor (TB1) producing the first image potential (VP), and the second branch with a resistor (R3) and a bipolar transistor (TB2) producing the second image potential (VM); and a comparator (COMP) producing a blocking or holding signal (POR) which is in a first logic state (active) when the first image potential (VP) is below the second iamge potential (VM), and in a second logic state (inactive) otherwise. The first image potential (VP) increases slowly with the supply potential, and the second image potential (VM) increases rapidly with the supply potential. The two image potentials are equal when the supply potential is equal to a characteristic constant of the circuit. Each bipolar transistor (TB1,TB2) has its base and its collector connected together to the ground. The two resistances (R2,R3) are equal. In a variant of the circuit (dotted line), a voltage divider bridge with two resistors (R4,R5) receives the supply potential (VDD) and produces a measure potential (VINT) which is proportional to the supply potential, and a capacitor (C) is connected in parallel with the two branches.

Patent Agency Ranking