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1.发明专利
公开(公告)号：FR2894694A1
公开(公告)日：2007-06-15
申请号：FR0512503
申请日：2005-12-09
Applicant: ST MICROELECTRONICS SA
Inventor： AYRIGNAC RENAUD , COLFER ANDREW , SENAME ISABELLE
Abstract: L'invention concerne un procédé de mise au point d'un programme multitâche exécuté par un processeur (µP), comprenant des étapes d'interruption du processeur durant l'exécution d'une tâche du programme, et d'activation d'un mode de mise au point du processeur, dans lequel les instructions (INST) exécutées par le processeur sont fournies par un émulateur externe (H). Selon l'invention, le procédé comprend des étapes au cours desquelles: le processeur (µP) émet vers l'émulateur externe (H) un message d'activation (DGM) à chaque fois que le mode de mise au point est activé, et à la réception du message d'activation, l'émulateur externe envoie au processeur un message d'accusé de réception (ADGM) contenant au moins une partie du message d'activation reçu.
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公开(公告)号：GB2362968B
公开(公告)日：2003-12-10
申请号：GB9930589
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , SENAME ISABELLE , BERNARD BRUNO , WOJCIESZAK LAURENT , DEHAMEL ARNAUD
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公开(公告)号：GB2362968A
公开(公告)日：2001-12-05
申请号：GB9930589
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , SENAME ISABELLE , BERNARD BRUNO , WOJCIESZAK LAURENT , DEHAMEL ARNAUD
Abstract: A system for executing instructions having assigned guard or prediction indicators, the system comprising instruction supply circuitry, at least one pipelined execution unit for receiving instructions from the supply circuitry together with a guard or prediction indicator selected from a set of guard or prediction indicators. The execution unit includes a master guard value store containing master values for the guard indicators and circuitry for resolving the guard or prediction value of the guard or prediction indicator in the instruction pipeline and providing a signal to indicate if the pipeline is committed to executing the instruction. The system includes an emulator which has watch circuitry for watching selected instructions in the execution pipeline and synchronising circuitry for correlating resolution of the guard or prediction indicator of each selected instruction with a program count for that instruction.
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公开(公告)号：FR2894693A1
公开(公告)日：2007-06-15
申请号：FR0512502
申请日：2005-12-09
Applicant: ST MICROELECTRONICS SA
Inventor： AYRIGNAC RENAUD , SENAME ISABELLE
Abstract: L'invention concerne un procédé d'exécution par un processeur d'une instruction de sauvegarde/restauration (PUSH #IM, POP #IM) de plusieurs registres (Ri) internes du processeur, comprenant des étapes de décomposition de l'instruction de sauvegarde/restauration pour générer des micro instructions de sauvegarde/restauration (PUSH Ri, POP Ri) du contenu d'un registre (Ri), et d'exécution de chacune des micro instructions. Selon l'invention, le procédé comprend des étapes d'initialisation d'un état d'avancement (PMSK) de la sauvegarde/restauration des registres (Ri), de mise à jour de l'état d'avancement de la sauvegarde/restauration à chaque génération d'une micro instruction de sauvegarde/restauration d'un registre (PUSH Ri, POP Ri), et de sauvegarde de l'état d'avancement en cas d'interruption de la sauvegarde/restauration des registres, pour exécuter une tâche plus prioritaire et de restauration de l'état d'avancement lors de la reprise de la sauvegarde/restauration des registres.
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公开(公告)号：GB2362730B
公开(公告)日：2004-02-11
申请号：GB9930590
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： WOJCIESZAK LAURENT , SENAME ISABELLE , BOUVIER STEPHANE
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Patent Agency Ranking
公开(公告)号：GB2362729B
公开(公告)日：2004-02-11
申请号：GB9930588
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , SENAME ISABELLE , BERNARD BRUNO
IPC: G06F9/38
Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.
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公开(公告)号：GB2366006B
公开(公告)日：2004-06-30
申请号：GB9930587
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , WOJCIESZAK LAURENT , SENAME ISABELLE
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公开(公告)号：GB2362730A
公开(公告)日：2001-11-28
申请号：GB9930590
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： WOJCIESZAK LAURENT , SENAME ISABELLE , BOUVIER STEPHANE
Abstract: A system for executing a sequence of instructions and effecting changes in data held in one or more registers during execution of the instructions, the system including instruction fetch circuitry, decode circuitry to decode instructions and identify registers used in the execution of the instruction and dispatch circuitry to send instructions to one or more execution units after decoding. The system also includes emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions. The circuitry further comprises a register watch store, for identifying registers to be watched, comparator circuitry, for comparing registers identified by the decode circuitry to registers identified by the register watch store and for recording a signal whenever these match and instruction insertion circuitry responsive to those signals to insert a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data register into the instruction queue for an execution unit.
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公开(公告)号：GB2362729A
公开(公告)日：2001-11-28
申请号：GB9930588
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , SENAME ISABELLE , BERNARD BRUNO
IPC: G06F9/38
Abstract: A system for executing pipelined instructions, the system including instruction fetch circuitry, instruction dispatch circuitry, data memory for use in store and load operations, data memory access circuitry and emulator circuitry for use in debug operations. The emulator circuitry includes circuitry indicating an error in the data memory access operation, snoop circuitry for snooping memory access in the data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with program counts for the instructions associated with the access addresses and memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.
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公开(公告)号：GB2365546B
公开(公告)日：2004-02-18
申请号：GB9930586
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , WOJCIESZAK LAURENT , SENAME ISABELLE
IPC: G06F11/36
Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be "killed" later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.
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