公开(公告)号：DE69813843D1

公开(公告)日：2003-05-28

申请号：DE69813843

申请日：1998-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： GALBIATI EZIO ,  PAPILLO LORENZO ,  CHRAPPAN SOLDAVINI FRANCESCO

IPC: G06F1/025 ,  H02M7/5387

Abstract: In driving a load in a PWM mode in function of numeric command values of a certain N number of bits by converting the current numeric command value in at least a driving PWM signal (PWM_A, PWM_B) having a fixed frequency and a duty cycle proportional to the numeric command value, comparing through a comparator (COMPARATOR) the N bit numeric value with the counter of an up/down counter of the same number (N) of bits (N BIT UP/DOWN COUNTER) functioning in a continuous mode at the frequency of a system's clock signal (SysClk), the definition of the conversion may be enhanced withtout correspondingly increasing the number of bits of the UP/DOWN COUNTER. This is achieved by incrementing by more than a unit (N+3) the number of bits on which a certain command value is mapped; converting the N most significant bits with the exception of said additional bits of said command value by means of said comparator and up/down counter; decoding said additional bits by generating a corresponding plurality of intermediate levels of variation of the duty cycle, each of which has a duration of half a clock period (SysClk/2) producing a plurality of signals, outphased among each other by half a clock period (A, B, C, D, B, A', B', C', D', E'); generating said driving PWM signal (IN_A, IN_B) by multiplating (MULTIPLEXER) said signals outphased among each other by half a clock period, carrying out logic combinations of such signals in function of the most significative bit (MSB) of the numeric command value and of said least significative additional bits.

公开(公告)号：DE69514918D1

公开(公告)日：2000-03-09

申请号：DE69514918

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

IPC: H03K3/037 ,  H03K3/3562

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

公开(公告)号：DE69514918T2

公开(公告)日：2000-06-15

申请号：DE69514918

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

IPC: H03K3/037 ,  H03K3/3562

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.