公开(公告)号：JPH11191991A

公开(公告)日：1999-07-13

申请号：JP28580198

申请日：1998-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI ANNAMARIA

IPC: H02P6/08 ,  H02P6/21 ,  H02P7/36

Abstract: PROBLEM TO BE SOLVED: To provide a synchronization circuit for simply and reliably switching from a closed loop mode to an open loop mode or vice versa. SOLUTION: A circuit has a programming resistor REG FT for programming a specific value of frequency for scanning the sample of a profile, a demultiplexer DEMU and a multiplexer MUX for inputting the output of the programming resistor to a first resistor REG A, and a circuit MSF FALSE for generating a compulsory synchronizing pulse for loading the data of the programming resistor to a first resistor during opened loop operation by a value, in which the counter value of a third counter CONTN is smaller than the number of samples by 1 and for generating a reset signal for resetting a first counter CONT UP, the multiplexer, and the demultiplexer.

公开(公告)号：JPH11136099A

公开(公告)日：1999-05-21

申请号：JP24622998

申请日：1998-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI ANNAMARIA ,  FUCILI GIONA ,  MARCELLO LEONE ,  NESSI MAURIZIO

IPC: H03K3/037 ,  H03K3/356

Abstract: PROBLEM TO BE SOLVED: To produce an XOR gate with use of a small number of transistors TR by connecting the output terminal of a flip-flop corresponding to the output terminal Q of a D type flip-flop to the gate terminal of a prescribed TR and also to a circuit node in a feedback way. SOLUTION: Only three TRs are used in addition to a TR consisting of a reference inverted input stage that is driven by the reference timing signals fi and Nfi (having non-superimposed phases). An XNOR input stage includes two TR M1 and M2 which are connected in series between an input terminal T and an output circuit node A via the source and drain terminals respectively. The gate terminal of the 1st TR M1 is connected to a node C, and the signal Nfi is applied to the gate terminal of the 2nd TR M2. Then a 3rd TR M3 is connected between a circuit power line Vdd and a circuit node B.

公开(公告)号：DE69713773T2

公开(公告)日：2002-10-17

申请号：DE69713773

申请日：1997-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI ANNAMARIA

IPC: H02P6/08 ,  H02P6/21 ,  H02P6/20 ,  H02P6/18

Abstract: The synchronizing circuit of a digital drive system of an electric motor is configured to function in a closed loop or in an open loop mode by adding a minimum number of elements to the normal scheme of a closed loop synchronizing circuit. In practice, by adding only one programmable register and a pair of two-input de-multiplexers, the system is able to automatically switch from one mode of operation to the other mode. The programmable open loop mode permits to compensate for the phase angle between the current flowing through the windings and the drive voltage applied thereto, in case of a voltage mode driving.

公开(公告)号：DE69725977D1

公开(公告)日：2003-12-11

申请号：DE69725977

申请日：1997-08-29

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI ANNAMARIA ,  FUCILI GIONA ,  CANE MARCELLO ,  NESSI MAURIZIO

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/00

Abstract: A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion. Three transistors (M1,M2,M3) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back.

公开(公告)号：DE69514918D1

公开(公告)日：2000-03-09

申请号：DE69514918

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

IPC: H03K3/037 ,  H03K3/3562

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

公开(公告)号：DE69713773D1

公开(公告)日：2002-08-08

申请号：DE69713773

申请日：1997-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI ANNAMARIA

IPC: H02P6/08 ,  H02P6/21 ,  H02P6/20 ,  H02P6/18

Abstract: The synchronizing circuit of a digital drive system of an electric motor is configured to function in a closed loop or in an open loop mode by adding a minimum number of elements to the normal scheme of a closed loop synchronizing circuit. In practice, by adding only one programmable register and a pair of two-input de-multiplexers, the system is able to automatically switch from one mode of operation to the other mode. The programmable open loop mode permits to compensate for the phase angle between the current flowing through the windings and the drive voltage applied thereto, in case of a voltage mode driving.

公开(公告)号：DE69514918T2

公开(公告)日：2000-06-15

申请号：DE69514918

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

IPC: H03K3/037 ,  H03K3/3562

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.