公开(公告)号：DE69514918D1

公开(公告)日：2000-03-09

申请号：DE69514918

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

IPC: H03K3/037 ,  H03K3/3562

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

公开(公告)号：DE69514918T2

公开(公告)日：2000-06-15

申请号：DE69514918

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

IPC: H03K3/037 ,  H03K3/3562

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.