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    DECODED COUNTER ENABLING ERROR CHECK AND SELF CORRECTION
    1.
    发明专利
    DECODED COUNTER ENABLING ERROR CHECK AND SELF CORRECTION 失效

    公开(公告)号：JPH0738421A

    公开(公告)日：1995-02-07

    申请号：JP16278894

    申请日：1994-06-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA

    IPC: H03K21/40 ,  H03M13/00

    Abstract: PURPOSE: To precisely perform self-correcting by making one of shift registers that include (n) pieces of FFs have a synchronous set, making all the rest have a synchronous reset and also having a pull-up line. CONSTITUTION: Only a 1st FF of a chain has asynchronous set and all the rest FFs have asynchronous resetting means. More than two FFs include one, and when a 1st one among these ones reaches the last FF of the chain, synchronous set-reset operation is automatically triggered, all the ones but one finally exist in the 1st FF and then go through an set input of the 1st FF. When an FF does not include one, entire switches that are driven by each FF are opened, then, a pull-up line has a high level through the pull-up device. Thereby, the 1st FF of the chain loads one through the D input at effective front where signals continue, and the precise state of a CRS operation is established again.

    LOGICAL NETWORK, BINARY DEVICE CONTAINING THE SAME AND SYNCHRONOUS DIVIDER DEVICE
    2.
    发明专利
    LOGICAL NETWORK, BINARY DEVICE CONTAINING THE SAME AND SYNCHRONOUS DIVIDER DEVICE 失效

    公开(公告)号：JPH11136099A

    公开(公告)日：1999-05-21

    申请号：JP24622998

    申请日：1998-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROSSI ANNAMARIA ,  FUCILI GIONA ,  MARCELLO LEONE ,  NESSI MAURIZIO

    IPC: H03K3/037 ,  H03K3/356

    Abstract: PROBLEM TO BE SOLVED: To produce an XOR gate with use of a small number of transistors TR by connecting the output terminal of a flip-flop corresponding to the output terminal Q of a D type flip-flop to the gate terminal of a prescribed TR and also to a circuit node in a feedback way. SOLUTION: Only three TRs are used in addition to a TR consisting of a reference inverted input stage that is driven by the reference timing signals fi and Nfi (having non-superimposed phases). An XNOR input stage includes two TR M1 and M2 which are connected in series between an input terminal T and an output circuit node A via the source and drain terminals respectively. The gate terminal of the 1st TR M1 is connected to a node C, and the signal Nfi is applied to the gate terminal of the 2nd TR M2. Then a 3rd TR M3 is connected between a circuit power line Vdd and a circuit node B.

    PROGRAMMABLE TIME-INTERVAL GENERATOR AND TIME-ENTERVAL GENERATING METHOD
    3.
    发明专利
    PROGRAMMABLE TIME-INTERVAL GENERATOR AND TIME-ENTERVAL GENERATING METHOD 失效

    公开(公告)号：JPH0792279A

    公开(公告)日：1995-04-07

    申请号：JP5921594

    申请日：1994-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA ,  NESSI MAURIZIO

    IPC: G04F5/00 ,  G06F1/025 ,  G06F7/62 ,  H02P6/08 ,  H03K5/13 ,  H03K21/38

    Abstract: PURPOSE: To provide a generator of programmable time interval by which the accuracy can be improved in comparison with a conventional digital generator. CONSTITUTION: The time interval generating device comprises the first and second digital counters 1, 5 a memory 2, a digital divider 3, and a digital adding machine 4, the counting is started by the counter 1 when the first event is generated, then only. the digit of higher position of a figure of the counted number, is memorized when the second event is generated, thereby the dividing by the omission, is performed. At least two separate fractions are obtained from the memorized number by the divider 3, and the fractions are added by the adding machine 4 operated in the binary digit string. The counter 5 counts down the sum to generate a signal at the clearing.

    4.
    发明专利
    未知

    公开(公告)号：DE69507126D1

    公开(公告)日：1999-02-18

    申请号：DE69507126

    申请日：1995-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA ,  NESSI MAURIZIO

    IPC: H02P7/03 ,  H02P7/00

    Abstract: Masking of switching noise is implemented in the driving system of an "H" bridge stage by exploiting the periodic signal generated by a PWM control circuit (normally present in the control system for controlling the "H" bridge in an open-loop mode) for masking the decay time of the disturbances caused by the switching from off-to-on of a first pair of switches of the bridge that drive a current in a certain direction through the load. This is implemented by keeping high for a preset period of time the periodic signal generated by the PWM circuit and varying the duty-cycle of the signal for regulating the mask time in function of the load characteristics. The system further comprises the masking of the decay interval of the disturbances caused by the switching from on-to-off of the first pair of switches and from off-to-on of the other pair of switches that provide a current ricirculation path of the energy stored in the reactance of the load, for a preset number of clock cycles, thus impeding any subsequent switching for the duration of this second mask. This second mask may be realised in different ways. The use of an up-counter and a programmable comparator been preferred.

    5.
    发明专利
    未知

    公开(公告)号：DE69725977D1

    公开(公告)日：2003-12-11

    申请号：DE69725977

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROSSI ANNAMARIA ,  FUCILI GIONA ,  CANE MARCELLO ,  NESSI MAURIZIO

    IPC: H03K3/037 ,  H03K3/356 ,  H03K3/00

    Abstract: A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion. Three transistors (M1,M2,M3) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back.

    8.
    发明专利
    未知

    公开(公告)号：DE69514918D1

    公开(公告)日：2000-03-09

    申请号：DE69514918

    申请日：1995-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

    IPC: H03K3/037 ,  H03K3/3562

    Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

    9.
    发明专利
    未知

    公开(公告)号：DE69514918T2

    公开(公告)日：2000-06-15

    申请号：DE69514918

    申请日：1995-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

    IPC: H03K3/037 ,  H03K3/3562

    Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

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