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    3.
    发明专利
    未知

    公开(公告)号：DE69514918T2

    公开(公告)日：2000-06-15

    申请号：DE69514918

    申请日：1995-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

    IPC: H03K3/037 ,  H03K3/3562

    Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

    4.
    发明专利
    未知

    公开(公告)号：DE69227106T2

    公开(公告)日：1999-04-01

    申请号：DE69227106

    申请日：1992-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DEMICHELI MARCO ,  GOLA ALBERTO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

    Abstract: A bias structure (30) for an integrated circuit comprising a first (31) and second (32) transistor having emitter terminals connected respectively to the supply (VCC) and to a terminal (35) of a resistor (6) whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source (34); and collector terminals connected electrically (12) to the epitaxial tub housing the resistor. A resistor (33) is preferably provided between the two collectors, so that, when the potential of the terminal (35) of the resistor (6) exceeds the supply voltage (VCC), the second transistor (32) saturates and maintains the epitaxial tub of the resistor (6) at a potential close to that of the resistor terminal (35), thus preventing the parasitic diode formed between the resistor (6) and the epitaxial tub from being switched on.

    5.
    发明专利
    未知

    公开(公告)号：AT171565T

    公开(公告)日：1998-10-15

    申请号：AT92830338

    申请日：1992-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DEMICHELI MARCO ,  GOLA ALBERTO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

    Abstract: A bias structure (30) for an integrated circuit comprising a first (31) and second (32) transistor having emitter terminals connected respectively to the supply (VCC) and to a terminal (35) of a resistor (6) whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source (34); and collector terminals connected electrically (12) to the epitaxial tub housing the resistor. A resistor (33) is preferably provided between the two collectors, so that, when the potential of the terminal (35) of the resistor (6) exceeds the supply voltage (VCC), the second transistor (32) saturates and maintains the epitaxial tub of the resistor (6) at a potential close to that of the resistor terminal (35), thus preventing the parasitic diode formed between the resistor (6) and the epitaxial tub from being switched on.

    6.
    发明专利
    未知

    公开(公告)号：ITMI20031248D0

    公开(公告)日：2003-06-20

    申请号：ITMI20031248

    申请日：2003-06-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BASCHIROTTO ANDREA ,  D AMICO STEFANO ,  GOLA ALBERTO

    IPC: H03H11/04 ,  H03K5/22

    Abstract: A continuous-time filter comprising at least one amplifier and at least one passive element. The amplifier comprises at least one input terminal and at least one output terminal and the passive element is positioned between the terminals. In addition the amplifier is provided with a transconductance gain. The filter comprises circuit means suitable for correlating the transconductance gain of the amplifier with the passive element.

    7.
    发明专利
    未知

    公开(公告)号：DE69227106D1

    公开(公告)日：1998-10-29

    申请号：DE69227106

    申请日：1992-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DEMICHELI MARCO ,  GOLA ALBERTO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

    Abstract: A bias structure (30) for an integrated circuit comprising a first (31) and second (32) transistor having emitter terminals connected respectively to the supply (VCC) and to a terminal (35) of a resistor (6) whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source (34); and collector terminals connected electrically (12) to the epitaxial tub housing the resistor. A resistor (33) is preferably provided between the two collectors, so that, when the potential of the terminal (35) of the resistor (6) exceeds the supply voltage (VCC), the second transistor (32) saturates and maintains the epitaxial tub of the resistor (6) at a potential close to that of the resistor terminal (35), thus preventing the parasitic diode formed between the resistor (6) and the epitaxial tub from being switched on.

    10.
    发明专利
    未知

    公开(公告)号：DE69514918D1

    公开(公告)日：2000-03-09

    申请号：DE69514918

    申请日：1995-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FUCILI GIONA ,  PAPILLO LORENZO ,  PASQUINO ANDREA ,  ROSSI ANNAMARIA ,  GOLA ALBERTO

    IPC: H03K3/037 ,  H03K3/3562

    Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

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