公开(公告)号：EP1043769A1

公开(公告)日：2000-10-11

申请号：EP99830199.8

申请日：1999-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fallica, Piero Giorgio ,  Patti, Davide Giuseppe ,  Rapisarda, Cirino

IPC: H01L21/762 ,  H01L21/763

CPC classification number: H01L21/76232 ,  H01L21/763

Abstract: The process comprises the steps of: carrying out a directional etching, in a semiconductor material body (2, 3), to form trenches (10, 10a) having a first width; carrying out an isotropic etching of the semiconductor material body (2, 3) under the trenches (10, lOa) to form cavities (13; 13a; 13b) having a width larger than the trenches; covering the walls of the cavities with dielectric material (17a; 17b; 17c); depositing non-conducting material different from thermal oxide to fill said cavities at least partially, so as to form a single-crystal island (16) separated from the rest of the semiconductor material body (2, 3). The isotropic etching permits the formation of at least two adjacent cavities (13a, 13b) separated by a support region (25) of semiconductor material which is oxidized (26) together with the walls of the cavities to provide a support to the island (16) prior to filling with non-conducting material.

Abstract translation: 该方法包括以下步骤：执行一方向性蚀刻，在半导体材料体（2，3），以形成沟槽（10，10A），其具有第一宽度; 进行半导体材料主体的各向同性蚀刻的（2，3）在沟槽下（10，图10a），以形成空腔（13; 13A; 13B），其具有的宽度大于所述沟槽较大; 覆盖有电介质材料的空腔的壁（17A; 17B; 17C）; 沉积非导电材料从热氧化物不同填充所述空腔至少部分地，以形成从所述半导体材料体的其余部分分离的单晶冰岛（16）（2，3）。 各向同性蚀刻允许至少两个相邻空腔的形成（13A，13B）由半导体材料制成的支承区域（25）中分离的所有被氧化（26）与腔室的壁以向冰岛的支撑一起（16 ）之前的非导电材料填充。

公开(公告)号：EP1635397A1

公开(公告)日：2006-03-15

申请号：EP04425681.6

申请日：2004-09-14

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide Giuseppe ,  Settanni, Giuditta

IPC: H01L29/06 ,  H01L27/02

CPC classification number: H01L29/0615

Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub1, (P_tub2, ...) of an integrated device must be realized may be effectively prevented.
This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (α) may be generally comprised between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

Abstract translation: 可以有效地防止在必须实现集成装置的主结（P_tub1，（P_tub2，...）的周边高压环延伸注入区域（RHV）的中断时产生的不稳定性和相关缺点，这一重要结果是 通过非常简单的方法实现：每当必须产生高压环延伸的中断（I）时，沿着与周边注入区域的共同的正交方向在其上没有实现直线，相反，窄间隔被定义 倾斜或倾斜地穿过周边高压环延伸部的宽度，在直线中断的情况下，倾斜角（±）通常可以在30度和60度之间，更优选地在45度或更接近， 当实现周边高压环延伸区域时，通过将其从掺杂剂注入掩蔽来产生窄中断。

公开(公告)号：EP2927929A1

公开(公告)日：2015-10-07

申请号：EP15159971.9

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide Giuseppe ,  Grasso, Gianleonardo

IPC: H01J21/10 ,  G01K7/00

CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

Abstract: An integrated vacuum microelectronic structure (1) is described which includes:
a highly doped semiconductor substrate (11),
a first insulating layer (12) placed above the doped semiconductor substrate (11),
a first conductive layer placed above the first insulating layer,
a second insulating layer (93) placed above the first conductive layer,
a vacuum trench (19) formed within the first and second insulating layers (12, 93) and extending to the highly doped semiconductor substrate (11),
a second conductive layer (42) placed above the vacuum trench and acting as a cathode,
a third conductive layer (22) placed under the highly doped semiconductor substrate (11) and acting as an anode,
the second conductive layer (42) is placed adjacent to the upper edge (40) of the vacuum trench (19),
wherein the first conductive layer is separated from the vacuum trench (19) by portions of the second insulating layer and is in electrical contact with the second conductive layer (42). (Fig. 1).

公开(公告)号：EP0756329B1

公开(公告)日：2002-01-16

申请号：EP95830328.1

申请日：1995-07-27

Applicant: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe ,  STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore ,  Lizzio, Pietro ,  Patti, Davide Giuseppe ,  Palara, Sergio

IPC: H01L29/732 ,  H01L29/10 ,  H01L21/331

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/7322

公开(公告)号：EP2927929B1

公开(公告)日：2016-09-07

申请号：EP15159971.9

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide Giuseppe ,  Grasso, Gianleonardo

IPC: H01J21/10 ,  G01K7/00

CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

Abstract: An integrated vacuum microelectronic structure (1) is described which includes: a highly doped semiconductor substrate (11), a first insulating layer (12) placed above the doped semiconductor substrate (11), a first conductive layer placed above the first insulating layer, a second insulating layer (93) placed above the first conductive layer, a vacuum trench (19) formed within the first and second insulating layers (12, 93) and extending to the highly doped semiconductor substrate (11), a second conductive layer (42) placed above the vacuum trench and acting as a cathode, a third conductive layer (22) placed under the highly doped semiconductor substrate (11) and acting as an anode, the second conductive layer (42) is placed adjacent to the upper edge (40) of the vacuum trench (19), wherein the first conductive layer is separated from the vacuum trench (19) by portions of the second insulating layer and is in electrical contact with the second conductive layer (42). (Fig. 1).

Abstract translation: 描述了一种集成的真空微电子结构（1），其包括：高掺杂半导体衬底（11），置于掺杂半导体衬底（11）上方的第一绝缘层（12），置于第一绝缘层上方的第一导电层， 放置在第一导电层上方的第二绝缘层（93），形成在第一和第二绝缘层（12,93）内并延伸到高掺杂半导体衬底（11）的真空沟槽（19），第二导电层 42）放置在真空沟槽上方并用作阴极，第三导电层（22）放置在高度掺杂的半导体衬底（11）下并用作阳极，第二导电层（42）被放置成与上边缘 （40），其中所述第一导电层通过所述第二绝缘层的一部分与所述真空沟槽（19）分离，并且与所述第二导电层（42）电接触。 （图。1）。