公开(公告)号：EP1139419A1

公开(公告)日：2001-10-04

申请号：EP00830236.6

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Peschiaroli, Daniela ,  Maurelli, Alfonso ,  Palumbo, Elisabetta ,  Piazza, Fausto

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: Method of manufacturing an integrated circuit comprising a memory operating at high voltage and logic circuitry operating at a lower voltage than the memory:
   formation of a first layer of gate oxide (3) with a first thickness on first and second portions of a semiconductor substrate (1) which are intended, respectively, for first transistors operating at high voltage and for second transistors operating at the lower voltage, and formation of a second layer of gate oxide (5) with a second thickness on third portions for cells of the memory; deposition of a first polysilicon layer to define gate electrodes (8,9) for first transistors and floating gate electrodes (7) for the memory cells; deposition of an interpolysilicon dielectric layer (18) so as to leave the interpolysilicon dielectric layer on the gate electrodes (8,9) of first transistors and on the floating gate electrodes (7); formation, on the second portions (1), of a third gate oxide layer (24) with a third thickness less than the first thickness of the first gate oxide layer (3); deposition of a second polysilicon layer (25) to define gate structures (29) of the memory cells, and gate electrodes (26,27) of second transistors and polysilicon covers (80,90) for the gate electrodes (8,9) of first transistors.

Abstract translation: 一种制造集成电路的方法，该集成电路包括在高电压下工作的存储器和在比该存储器低的电压下操作的逻辑电路：在半导体衬底的第一和第二部分上形成具有第一厚度的栅极氧化物（3）的第一层 1），其分别用于在高电压下操作的第一晶体管和用于在较低电压下操作的第二晶体管，以及在存储器的单元的第三部分上形成具有第二厚度的栅极氧化物（5）的第二层; 沉积第一多晶硅层以限定用于第一晶体管的栅电极（8,9）和用于存储器单元的浮栅电极（7）; 沉积多晶硅介电层（18），以便在第一晶体管的栅电极（8,9）和浮栅电极（7）上留下多晶硅介电层; 在第二部分（1）上形成具有小于第一栅极氧化物层（3）的第一厚度的第三厚度的第三栅极氧化物层（24）; 沉积第二多晶硅层（25）以限定存储器单元的栅极结构（29），以及第二晶体管的栅电极（26,27）和用于栅电极（8,9）的多晶硅覆盖物（80,90） 第一晶体管。

公开(公告)号：EP1526568B1

公开(公告)日：2009-02-25

申请号：EP03425687.5

申请日：2003-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Zabberoni, Paola

IPC: H01L21/8247 ,  H01L21/8234

CPC classification number: H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1863089A1

公开(公告)日：2007-12-05

申请号：EP06425371.9

申请日：2006-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Piazza, Fausto ,  Vigiani, Carlo ,  Zabberoni, Paola

IPC: H01L27/105 ,  H01L27/02 ,  H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11534

Abstract: A method is described for manufacturing electrically non active structures of an integrated electronic circuit (1) formed on a semiconductor substrate (7) comprising first electrically active structures (2) which comprise electric components provided with conductive elements (16) of a first height (H1) projecting from said semiconductor substrate (7) and second electrically active structures (3) which comprise electric components provided with conductive elements (20) of a second height (H2) projecting from said semiconductor substrate (7), said first height being different from said second height, the method comprising the steps of:
- introducing, into the integrated electronic circuit (1), electrically non active structures (4) to superficially uniform the integrated electronic circuit (1),
- identifying, between the electrically non active structures (4), a first group (5) of electrically non active structures which is formed by those electrically non active structures comprised in areas (5a) which substantially extend for a predetermined radius (R) around each electric component belonging to the second electrically active structures (3),
- identifying, between the electrically non active structures (4), a second group (6) of electrically non active structures comprising electrically non active structures not belonging to the first group (5) of electrically non active structures,
- forming the electrically non active structures belonging to the first group (5) of electrically non active structures with elements (20a) projecting from the substrate (7) having a height equal to the second height (H2),
- forming the electrically non active structures belonging to the second group (6) of electrically non active structures with elements (16a) projecting from the substrate (7) having a height equal to the first height (H1), the elements (16a, 20a) belonging to the first (5) and second group (6) of electrically non active structures being formed by means of respective photolithographic steps.

Abstract translation: 描述了一种用于制造形成在半导体衬底（7）上的集成电子电路（1）的非电活动结构的方法，所述电子电路包括第一电活性结构（2），所述第一电活性结构（2）包括设置有第一高度的导电元件（16） H1）和第二电活动结构（3），所述第二电活性结构（3）包括设置有从所述半导体衬底（7）突出的第二高度（H2）的导电元件（20）的电气部件，所述第一高度不同 从所述第二高度，所述方法包括以下步骤：将集成电子电路（1）引入电非活动结构（4）以使所述集成电子电路（1）表面均匀; - 识别所述电非活动 结构（4），由非电活性结构组成的第一组（5），由非电活性结构构成 围绕属于第二电活动结构（3）的每个电气部件围绕预定半径（R）延伸的区域（5a）， - 识别在电非活性结构（4）之间的电子非活性结构（4）的第二组（6） 非活性结构包括不属于电非活性结构的第一组（5）的非电活性结构， - 形成属于电非活性结构的第一组（5）的非电活性结构，其中元件（20a）从 所述衬底（7）具有等于所述第二高度（H2）的高度， - 形成属于所述第二组（6）的电非活性结构的电非活性结构，其中从所述衬底（7）突出的元件（16a） 属于第一高度（H1）的高度，属于非活性结构的第一组（5）和第二组（6）的元件（16a，20a）通过相应的ph形成 光刻步骤。

公开(公告)号：EP1109217A1

公开(公告)日：2001-06-20

申请号：EP99830770.6

申请日：1999-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Palumbo, Elisabetta ,  Peschiaroli, Daniela ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

Abstract: The body regions for the n-channel and p-channel LV transistors, for the n-channel HV transistors, and for the EPROM cells are formed on a silicon substrate; a thermal oxide layer (12) is formed and a layer of polycrystalline silicon (13) is formed thereon; the latter layer is selectively removed to form the floating gate electrodes (13a) of the cells and the gate electrodes (13b) of the HV transistors; the source and drain regions (14) of the cells, the source and drain regions (22) of the n-channel HV transistors, the body regions (24) and the source and drain regions of the p-channel HV transistors are formed; an ONO composite layer (15) is formed; the silicon of the areas of the LV transistors is exposed; a thermal oxide layer (16) is formed on the exposed areas; a second polycrystalline silicon layer (17) is deposited and is then removed selectively to form the gate electrodes of the LV transistors (17c) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV transistors are formed.
By virtue of the use of a material (ONO) which is impermeable to the oxygen atoms of the subsequent thermal oxidation and because the body regions (24) of the p-channel HV transistors and the source and drain regions of all of the HV transistors are produced by separate implantations, components of very good quality are produced with few more masks than a conventional LV method.

Abstract translation: 用于n沟道HV晶体管的n沟道和p沟道LV晶体管的主体区域和用于EPROM单元的体区域形成在硅衬底上; 形成热氧化物层（12），并在其上形成多晶硅层（13）; 选择性地去除后一层以形成单元的浮置栅电极（13a）和HV晶体管的栅电极（13b）; 形成单元的源极和漏极区域（14），n沟道HV晶体管的源极和漏极区域（22），体区域（24）以及p沟道HV晶体管的源极和漏极区域; 形成ONO复合层（15）; 暴露出LV晶体管的区域的硅; 在暴露的区域上形成热氧化层（16）; 沉积第二多晶硅层（17），然后选择性地去除以形成单元的LV晶体管（17c）和控制栅电极（17a）的栅电极，并且LV晶体管的源极和漏极区域 形成。 由于使用对随后的热氧化的氧原子不可渗透的材料（ONO），并且由于p沟道HV晶体管的体区（24）和所有HV晶体管的源极和漏极区域 通过单独的注入产生，非常好质量的组分以比常规LV方法少得多的掩模产生。

公开(公告)号：EP1526568A1

公开(公告)日：2005-04-27

申请号：EP03425687.5

申请日：2003-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Zabberoni, Paola

IPC: H01L21/8247 ,  H01L21/8234

CPC classification number: H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:

forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),
forming a second conductive layer (11) on a second portion of semiconductor substrate (1),
defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),
forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),
defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),
forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).

Abstract translation: 用于密封形成在半导体衬底上的电子器件的方法包括：形成与半导体衬底的第一部分相邻的多个第一电子器件，其中每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。 邻近第一区域形成第一密封层，用于密封多个第一电子器件。 在第一密封层附近形成保护层。 蚀刻保护层以形成与第一区域的侧壁相邻的保护性间隔物。 该方法还包括在半导体衬底的第二部分附近形成多个第二电子器件，每个第二电子器件包括第二区域，该第二区域包括从半导体衬底突出的第二导电层。 第二密封层邻近第二区域形成，用于密封多个第二电子器件，并邻近第一密封层以密封多个第一电子器件。

公开(公告)号：EP1104022A1

公开(公告)日：2001-05-30

申请号：EP99830742.5

申请日：1999-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbera ,  Peschiaroli, Daniela ,  Palumbo, Elisabetta ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11539 ,  Y10S438/981

Abstract: The active areas and the body regions for the LV MOS transistors, for the HV MOS transistors and for the EPROM cells are formed on a silicon substrate, a layer of thermal oxide is formed, and a layer of polycrystalline silicon is formed on it, the last-mentioned layer is removed selectively to form the floating gate electrodes (13a) of the cells, the source and drain regions of the cells are formed, the silicon of the areas of the HV MOS transistors is exposed, a layer of HTO oxide is formed and nitrided, the silicon of the areas of the LV MOS transistors is exposed, a layer of thermal oxide (16) is formed on the exposed areas, a second layer of polycrystalline silicon is deposited and is then removed selectively to form the gate electrodes of the LV and HV MOS transistors (17c, 17b) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV and HV MOS transistors are formed. Owing to the simultaneous formation of the gate dielectric of the HV MOS transistors and the intermediate dielectric of the cells, and the use of a material (nitrided HTO oxide) which is impermeable to the oxygen atoms of the subsequent thermal oxidation, the number of the operations in the process is smaller than in the prior art process.

Abstract translation: 有源区和用于LV MOS晶体管的体区，用于HV MOS晶体管和用于EPROM细胞在一个硅衬底上形成时，热氧化物的层被形成，和多晶硅层形成在其上，所述 最后提到的层被选择性地移除以形成所述单元的浮置栅电极（13A），该单元的源区和漏区上形成时，HV MOS晶体管的区域中的硅被暴露，HTO氧化物层是 形成，并且氮化中，LV MOS晶体管的区域中的硅被暴露，热氧化层（16）形成在暴露区域，多晶硅的第二层被沉积，然后除去有选择地形成栅电极 LV和HV MOS晶体管（17C，17B）和所述单元的控制栅电极（17A），和LV和HV MOS晶体管的源区和漏区的形成。 由于HV MOS晶体管的栅极电介质和细胞的中间电介质，以及使用的材料（氮化HTO氧化物）的所有不透随后的热氧化的氧原子，的数的同时形成 在这个过程中的操作比现有技术的方法要小。

公开(公告)号：EP1104021A1

公开(公告)日：2001-05-30

申请号：EP99830741.7

申请日：1999-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Palumbo, Elisabetta ,  Peschiaroli, Daniela ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11546

Abstract: The active areas and the body regions for the LV MOS transistors, for the HV MOS transistors and for the EPROM cells are formed on a silicon substrate, a layer of thermal oxide (12) is formed and a layer of polycrystalline silicon (13) is formed on it, the last-mentioned layer is removed selectively to form the floating gate electrodes (13a) of the cells, the source and drain regions (14) of the cells are formed, a composite ONO layer (15) is formed, the silicon of the areas of the LV MOS transistors is exposed, a layer of thermal oxide (16) is formed on the exposed areas, a second layer of polycrystalline silicon (17) is deposited and is then removed selectively to form the gate electrodes of the LV and HV MOS transistors (17c, 17b) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV and HV MOS transistors are formed.
Owing to the simultaneous formation of part of the gate dielectric of the HV MOS transistors and the intermediate dielectric of the cells, and the use of a material (ONO) which is impermeable to the oxygen atoms of the subsequent thermal oxidation, the number of the operations in the process is smaller than in the prior art process.

Abstract translation: 有源区和用于LV MOS晶体管的体区，用于HV MOS晶体管和用于EPROM单元形成在硅衬底上，热氧化层（12）被形成和多晶硅（13）的层是 在其上形成，最后提到的层被选择性地去除，以形成细胞的细胞，所述源和漏区（14）的浮栅电极（13A）的部分，复合ONO层（15）形成，所述 所述LV MOS晶体管的区域的硅被暴露，热氧化层（16）形成在暴露区域，多晶硅的第二层（17）被沉积，然后除去有选择地形成的栅极电极 LV和HV MOS晶体管（17C，17B）和所述单元的控制栅电极（17A），和LV和HV MOS晶体管的源极和漏极区域形成。 由于同时形成的HV MOS晶体管的栅极电介质和细胞的中间电介质，以及使用的材料（ONO）的组成部分的所有不透随后的热氧化的氧原子，的数 在这个过程中的操作比现有技术的方法要小。