中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.04 seconds)

    Process for cutting trenches in a single crystal substrate
    1.
    发明公开
    Process for cutting trenches in a single crystal substrate 失效
    Verfahren zur Herstellung vonGerätenin einem halbleitenden Substrat

    公开(公告)号：EP0889505A1

    公开(公告)日：1999-01-07

    申请号：EP97830335.2

    申请日：1997-07-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Queirolo, Giuseppe ,  Ottaviani, Giampiero ,  Cerofolini, Gianfranco

    IPC: H01L21/306

    CPC classification number: H01L21/306 ,  H01L21/3043

    Abstract: A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines the etch area on the surface of a monocrystallin silicon wafer eventually covered by a thin layer of oxide; implanting ions with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region; and heating the implanted wafer causing dislodgment and expulsion of the amorphized portion in correspondence of the interface with the adjacent crystal lattice of the silicon.

    Abstract translation: 在由掩模限定的区域中切割硅单晶中的沟槽的工艺包括形成掩模，其限定最终被薄层氧化物覆盖的单晶硅晶片的表面上的蚀刻区域; 以足够的动能注入离子并使剂量足以将硅非晶硅降低到限定区域内的预定深度，同时保持晶片的温度足够低以防止在硅中产生的点缺陷的弛豫和注入离子的扩散 在与非晶化区相邻的硅的晶格中; 并且加热植入的晶片，导致对应于与硅的相邻晶格的界面的非晶化部分的移动和排出。

    Integrated structure comprising a polysilicon element with large grain size
    2.
    发明公开
    Integrated structure comprising a polysilicon element with large grain size 失效
    Integrierte Struktur mit einem Bauelement ausgrobkörnigemPolysilizium

    公开(公告)号：EP0877416A1

    公开(公告)日：1998-11-11

    申请号：EP97830212.3

    申请日：1997-05-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Queirolo, Giuseppe ,  Ferroni, Giovanni

    IPC: H01L21/20 ,  H01L21/3205 ,  H01L21/205 ,  H01L29/423 ,  H01L21/8247 ,  H01L29/92 ,  C23C16/24

    CPC classification number: H01L28/82 ,  C23C16/24 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/3205

    Abstract: The electrical performances of a dielectric film of capacitive coupling in an integrated structure are enhanced by forming the polycrystalline-metal electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. A process of forming a polycrystalline silicon film having exceptionally large grains of a size of the same order of magnitude of the dimensions of the patterned details is disclosed. These exceptionally large grains are obtained by preventing the formation of "precursor nuclei" of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

    Abstract translation: 一体化结构中的电容耦合介电膜的电性能通过在耦合区域上形成与电介质膜基本上单晶的多晶金属导电层而增强，通常由图案化叠层的电介质层和导电层来限定。 公开了一种形成具有与图案化细节的尺寸相同数量级的尺寸异常大的晶粒的多晶硅膜的工艺。 这些特别大的晶粒是通过防止在与CVD电沉积的第一时刻显而易见地形成的电介质的沉积界面处形成后续晶粒形成和生长的“前体核”，并且通过依次将微晶足够低地生长 退火温度。

Patent Agency Ranking