公开(公告)号：EP1788765A1

公开(公告)日：2007-05-23

申请号：EP05425816.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Nava, Claudio ,  Laurent, Christophe

IPC: H04L25/02 ,  H04B3/56

CPC classification number: H04L25/0266 ,  H04B3/56 ,  H04B2203/5487

Abstract: A transmission system of a digital signal is described of the type comprising a transmitter and a receiver connected by means of a transfer bus. The transmission system comprises at least one conductive line capacitively coupled with said transfer bus.

Abstract translation: 描述了数字信号的传输系统，其类型包括通过传输总线连接的发射机和接收机。 传输系统包括与所述传输总线电容耦合的至少一个导线。

公开(公告)号：EP1505605A1

公开(公告)日：2005-02-09

申请号：EP03017939.4

申请日：2003-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Fiorina, Sara ,  Bolandrina, Efrem ,  Schippers, Stefan ,  Onorato, Marco

IPC: G11C7/06 ,  G11C7/12 ,  G11C16/28 ,  G11C16/24

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C16/24 ,  G11C16/28

Abstract: A sensing circuit (101;301) for a semiconductor memory comprising a circuit branch (109;309) intended to be electrically coupled to a memory bit line (BL) having connected thereto a memory cell (MC) to be sensed. A bit line precharge circuit (117;317) is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit (117;317) is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop (119,N4;327,R), for controlling the memory bit line potential during the precharge phase. A same circuit element (119;327,R) is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

Abstract translation: 一种用于半导体存储器，其包括一电路支路（109; 309）;感测电路（301 101），用于被电耦合到存储器的位线（BL），其具有与其连接的存储单元（MC）将被感测。 位线预充电电路（117; 317）被提供，用于预充电的存储器的位线到预定电势中的存储器单元的感测操作的预充电阶段。 评估电路（117; 317）与所述存储器的位线相关联，用于在存储单元感测操作的评估阶段期间电量在存储器位线的发展评价; 电量没有开发出在存储器位线指示所述存储器单元中的信息内容。 位线预充电电路是angepasst到两个充电和放电的存储位线，所以DASS模具预定到达位线电位无关的存储器位线的初始电位的预充电阶段的开始。 位线预充电电路是angepasst到两个充电和放电的存储位线，这取决于存储器位线电位和预定位线电位之间的差。 至少所述预充电电路包括：预充电的负反馈控制环（119，N4，327，R），用于在预充电阶段控制所述存储器位线电位。 同一电路元件;设置（119 327，R）预充电阶段期间没有控制存储器位线电位，并在该存储单元读出操作的评估阶段评估电量。

公开(公告)号：EP1408604A1

公开(公告)日：2004-04-14

申请号：EP02425616.6

申请日：2002-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A charge pump (120) with current peak noise reduction is proposed. The charge pump includes a sequence of capacitive blocks (215) and means (225,240-250) for selectively transferring electric charge from each capacitive block to a next capacitive block, the means for transferring of each pair of adjacent capacitive blocks being enabled alternatively during a first phase and a second phase, respectively; the charge pump of the invention further includes means (255) for limiting a current flowing through each capacitive block during the first phase and the second phase.

Abstract translation: 几个电荷转移装置（225,240,250）在第一阶段和第二阶段期间选​​择性地和交替地将电荷从每个电容块（215）转移到下一个电容块。 电流限制器（255）在每个阶段控制每个电容块的电流。 还包括以下的依赖性权利要求：（a）非易失性存储装置; 和（b）电荷泵的操作方法。

公开(公告)号：EP1699054A1

公开(公告)日：2006-09-06

申请号：EP05101659.0

申请日：2005-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Bolandrina, Efrem

IPC: G11C11/56 ,  G11C16/28

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634 ,  G11C2211/5645

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc), means for comparing a set of selected memory cells (Mc) with at least one reference cell (Mr 0 -Mr 2 ) having a predefined threshold voltage, the means for comparing including biasing means (115) for applying a biasing voltage having a substantially monotone time pattern to the selected memory cells and the at least one reference cell, means (130) for detecting the reaching of a comparison current by a measure cell current corresponding to each selected memory cell and by a measure reference current corresponding to each reference cell, and means (145) for determining a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding measure cell current and by the at least one measure reference current, wherein the means for comparing further includes means (320-350;420-480;520-530;610) for selectively modifying at least one of said currents to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract translation: 提出了一种存储装置（100）。 存储器件包括多个存储器单元（Mc），用于将所选择的存储器单元（Mc）与至少一个具有预定阈值电压的参考单元（Mr 0 -Mr 2）进行比较的装置，用于比较的装置包括偏置 用于向所选择的存储单元和所述至少一个参考单元施加具有基本单调时间图案的偏置电压的装置（115），用于检测通过与每个所选存储器相对应的测量单元电流来达到比较电流的装置（130） 以及对应于每个参考单元的测量参考电流以及用于根据相应的测量单元电流达到比较电流的时间关系以及至少由所述至少一个测量单元电流确定每个所选存储单元的状态的装置（145） 一个测量参考电流，其中用于比较的装置还包括用于选择性地修改至少一个所述电流以模拟所述电流的装置（320-350; 420-480; 520-530; 610） 与至少一个具有另外阈值电压的另外的参考电池进行比较。

公开(公告)号：EP1467377B1

公开(公告)日：2007-11-28

申请号：EP03425224.7

申请日：2003-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

公开(公告)号：EP1835618A1

公开(公告)日：2007-09-19

申请号：EP06425173.9

申请日：2006-03-16

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Villa, Corrado ,  Zambelli, Yuri

IPC: H03K5/15 ,  G06F1/10

CPC classification number: H03K5/15013

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to a plurality of synchronizing and/or enabling circuits for performing a transfer of data to and from an integrated device, can be significantly reduced by having the external signal applied on a pad distributed unbuffered through a metal line of sufficiently large size (conductivity) such to introduce a negligible intrinsic propagation delay, though fulfilling the specified maximum admitted input pad capacitance, and by realizing locally dedicated input buffers to each of a plurality of synchronizing and/or enabling circuits of data transfer of the integrated device for applying thereto a buffered replica of the external signal present on said distributing metal line.

Abstract translation: 通过在INPUTBUFFER和由含金属的引入累积延迟的贡献没有分配缓冲的外部控制信号，以同步和/或使能电路在集成设备执行传输数据的向和从的复数，可以显着地由具有减少的 应用上的焊盘的外部信号通过寻求以引入可忽略的固有传播延迟足够大的尺寸（导电率）的金属线分布缓冲，虽然满足规定的最大承认输入衬垫电容，并且通过实现本地专用输入缓冲器的每一个的多个 的同步和/或使该集成器件的数据传送电路，用于向其施加存在于所述分配含金属的外部信号的缓冲的复制品。

公开(公告)号：EP1699055A1

公开(公告)日：2006-09-06

申请号：EP05101660.8

申请日：2005-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Bolandrina, Efrem ,  Vimercati, Daniele

IPC: G11C11/56 ,  G11C16/28

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

Abstract: A memory device (100;400) is proposed. The memory device includes a plurality of memory cells (Mc), means (115-145) for comparing a set of selected memory cells with at least one reference cell (Mr 0 -Mr 2 ;Mr) having a predefined threshold voltage, the means for comparing including means (115,120) for applying a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, means (130) for detecting the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, and logic means (145) for determining a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, wherein the means for comparing further includes means (220;520 j ;320 o -320 2 ,322;620 j ,622 j ) for time shifting at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract translation: 提出了存储器件（100; 400）。 存储器件包括多个存储器单元（Mc），用于将所选择的存储单元组与至少一个具有预定阈值电压的参考单元（Mr 0 -Mr 2; Mr）进行比较的装置（115-145） 用于比较包括用于将具有基本上单调的时间模式的偏置电压施加到所选择的存储器单元的装置（115,120）和至少一个参考单元，用于检测比较电流达到各个电池电流的装置（130） 选择的存储单元和每个参考单元的参考电流;以及逻辑单元（145），用于根据比较电流达到相应的单元电流的时间关系和至少至少 一个参考电流，其中用于比较的装置进一步包括用于根据至少一个预定间隔到emu的时间移位所述检测中的至少一个的装置（220; 520j; 320o-3202,322; 620j，622j） 迟到与具有另一阈值电压的至少一个另外的参考单元的比较。

公开(公告)号：EP1484764A1

公开(公告)日：2004-12-08

申请号：EP03425353.4

申请日：2003-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Schippers, Stefan ,  Vimercati, Daniele ,  Bolandrina, Efrem

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

Abstract: A method is described for generating a reference current (Iref) for sense amplifiers (11) connected to cells (12) of a memory matrix (1) comprising the steps of:

generating a first reference current analogue signal (REF) through a reference cell (14).

Advantageously according to the invention, the method further comprises the steps of:

performing an Analog-to-Digital conversion of the first analogue signal (REF) into a reference current digital signal (REF_BIT[3:0]);
sending the digital signal (REF_BIT[3:0]) on a connection line (43) to the sense amplifiers (11); and
performing a Digital-to-Analog conversion of the digital signal (REF_BIT[3:0]) into a second reference current analogue signal (REF1) to be applied as reference current (Iref) to the sense amplifiers (11).

The invention also relates to a reference current generator effective to implement this method.

Abstract translation: 描述了一种方法，用于产生连接到存储器矩阵的单元（12），用于读出放大器的参考电流（IREF）（11）（1），包括以下步骤：通过一个参考单元产生第一参考电流的模拟信号（REF） （14）。 有利地gemäß到本发明，该方法还包括以下步骤：执行在模拟到数字的第一模拟信号（REF）成参考电流数字信号（REF_BITÄ3：0U）的转换; 上的连接线（43）连接到读出放大器（11）：（0UREF_BITÄ3）;将所述数字信号 和执行数字信号（REF_BITÄ3：0U）的数字 - 模拟转换为第二参考电流的模拟信号（REF1）作为要应用的基准电流（I REF）到读出放大器（11）。 本发明因此涉及到参考电流发生器有效地实现此方法。

公开(公告)号：EP1473738B1

公开(公告)日：2009-11-04

申请号：EP03425264.3

申请日：2003-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Mirichigni, Graziano ,  Villa, Corrado

IPC: G11C16/08 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C16/08

公开(公告)号：EP1473738A1

公开(公告)日：2004-11-03

申请号：EP03425264.3

申请日：2003-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Mirichigni, Graziano ,  Villa, Corrado

IPC: G11C16/08 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C16/08

Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract translation: 一种电路（300）提出了一种用于驱动控制的非易失性存储器装置（100）中的至少一个存储单元（105）的存储器线（110），该电路响应于第一和第二选择信号，每一个 适合于采用第一逻辑值，或第二逻辑值，worin电路包括用于将第一选择信号转换成第一操作信号和用于第二选择信号转换为第二电平移位器（120克）第一电平移位器（120秒） 的第二操作信号，各电平移位器包括用于移动相应的选择信号的逻辑值中的一个到第一偏置电压的第一移位装置（210S，210克），以及用于将所述第一操作信号或第二选择器（140） 偏置电压施加到所述存储器线gemäß到所述第二操作信号; 在发明的电路中的每个电平移位器还包括第二移动装置（305S，305克），用于另一个相应的选择信号的逻辑值的转移到第二偏置电压。