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1.发明公开IMPROVED VACUUM INTEGRATED ELECTRONIC DEVICE AND MANUFACTURING PROCESS THEREOF 审中-公开改进的真空集成电子器件及其制造工艺
公开(公告)号：EP3171387A1
公开(公告)日：2017-05-24
申请号：EP16194697.5
申请日：2016-10-19
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Pte Ltd.
Inventor： PATTI, Davide Giuseppe , KIM, Myung Sung
CPC classification number: H01J19/02 , H01J9/025 , H01J9/18 , H01J21/04 , H01J21/105 , H01J21/20 , H01J2209/012 , H01J2209/02
Abstract: A vacuum integrated electronic device (120) has an anode region (101) of conductive material; an insulating region (102, 104) on top of the anode region; a cavity (54) extending through the insulating region and having a sidewall (53); and a cathode region (109). The cathode region has a tip portion (51, 52) extending peripherally within the cavity, adjacent to the sidewall of the cavity. The cathode region is formed by tilted deposition, carried out at an angle of 30-60° with respect to a perpendicular to the surface of device.
Abstract translation: 真空集成电子器件（120）具有导电材料的阳极区域（101） 在所述阳极区域的顶部上的绝缘区域（102,104） 延伸穿过绝缘区域并具有侧壁（53）的空腔（54）; 和阴极区（109）。 阴极区具有在空腔内沿周边延伸的邻近空腔侧壁的尖端部分（51,52）。 阴极区域通过倾斜沉积形成，相对于器件表面的垂线以30-60°的角度进行。
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2.发明授权
公开(公告)号：EP3462508B1
公开(公告)日：2020-08-12
申请号：EP18197797.6
申请日：2018-09-28
Applicant: STMicroelectronics S.r.l.
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公开(公告)号：EP3686923A1
公开(公告)日：2020-07-29
申请号：EP20154200.8
申请日：2020-01-28
Applicant: STMicroelectronics S.r.l.
Inventor： PATTI, Davide Giuseppe , ALEO, Mario Antonio
IPC: H01L21/762 , H01L27/02 , H01L21/8258 , H01L21/8234
Abstract: A semiconductor die (1) comprising: a structural body (3) including a power region (1b) and a peripheral region (1a), surrounding the power region (1b); at least one power device (10) in the power region (1b); and trench-insulation means (12), extending in the structural body (3) starting from the front side towards the back side along a first direction (Z), adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction (X) orthogonal to the first direction (Z). The trench-insulation means (12) have an extension (d), in the second direction (X), greater than the thickness (h) of the structural body along the first direction (Z).
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4.发明公开
公开(公告)号：EP3396718A1
公开(公告)日：2018-10-31
申请号：EP18168154.5
申请日：2018-04-19
Applicant: STMicroelectronics S.r.l.
Inventor： PATTI, Davide Giuseppe
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L27/0251 , H01L29/1095 , H01L29/41766 , H01L29/66696 , H01L29/66734 , H01L29/7803 , H01L29/7809 , H01L29/7813 , H01L29/7815
Abstract: Power MOS device (10), wherein a power MOS transistor (12) has a drain terminal coupled to a power supply node (17), a gate terminal coupled to a drive node (16) and a source terminal coupled to a load node (11). A detection MOS transistor (13) has a drain terminal coupled to a detection node (18), a gate terminal coupled to the drive node (16) and a source terminal coupled to the load node (11). A detection resistor (14) has a first terminal coupled to the power supply node (17) and a second terminal coupled to the detection node (18).
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公开(公告)号：EP3511988A1
公开(公告)日：2019-07-17
申请号：EP19151957.8
申请日：2019-01-15
Applicant: STMicroelectronics S.r.l.
Inventor： PATTI, Davide Giuseppe , SAMBI, Marco , TOIA, Fabrizio Fausto Renzo , MARIANI, Simone Dario , PIZZI, Elisabetta , BARILLARO, Giuseppe
IPC: H01L29/78 , H01L29/739 , H01L21/02
Abstract: A vertical-conduction semiconductor electronic device (40, comprising: a semiconductor body (1, 2); a body region (30) in the semiconductor body (1, 2); a source terminal (32) in the body region (30); a drain terminal (38) spatially opposite to the source region; and a trench gate (6, 14, 16', 24) extending in depth in the semiconductor body through the body region (30) and the source region (32). The trench gate includes a dielectric region (14) of porous silicon oxide buried in the semiconductor body, and a gate conductive region (24) extending between the dielectric region (14) of porous silicon oxide and said first side (2a).
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Patent Agency Ranking6.发明公开
公开(公告)号：EP3462508A3
公开(公告)日：2019-05-29
申请号：EP18197797.6
申请日：2018-09-28
Applicant: STMicroelectronics S.r.l.
Abstract: A capacitor (21; 31; 41) comprising: a substrate (22); a bottom plate, which extends over the substrate and includes a first conductive layer (28); a top plate, which extends over the bottom plate and includes a second conductive layer (46); a contact region (42), electrically coupled to the first conductive layer (28); and a first dielectric layer (38) including a first dielectric region (48), which extends between the bottom plate and the top plate, and a second dielectric region, which extends between the first dielectric region and the contact region (42), the first and second dielectric regions being adjacent to one another. The second dielectric region has a surface (38a) having a plurality of grooves designed to increase the extension of a surface path between the second conductive layer (46) and the contact region (42).
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公开(公告)号：EP3690928A1
公开(公告)日：2020-08-05
申请号：EP20154416.0
申请日：2020-01-29
Applicant: STMicroelectronics S.r.l.
Inventor： PATTI, Davide Giuseppe
IPC: H01L21/8258 , H01L27/06 , H01L27/088 , H01L21/8234 , H01L27/085
Abstract: The power device is formed by a D-mode HEMT (2) and by a MOSFET (3) in cascade to each other and integrated in a chip (51) having a base body (16) and a heterostructure layer (17) on the base body. The D-mode HEMT (2) comprises a channel area formed in the heterostructure layer; the MOSFET (3) comprises a first and a second conduction region (20, 21) formed in the base body, and an insulated-gate region (33A, 33B) formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region (25) extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region (20).
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8.发明公开
公开(公告)号：EP3462508A2
公开(公告)日：2019-04-03
申请号：EP18197797.6
申请日：2018-09-28
Applicant: STMicroelectronics S.r.l.
Abstract: A capacitor (21; 31; 41) comprising: a substrate (22); a bottom plate, which extends over the substrate and includes a first conductive layer (28); a top plate, which extends over the bottom plate and includes a second conductive layer (46); a contact region (42), electrically coupled to the first conductive layer (28); and a first dielectric layer (38) including a first dielectric region (48), which extends between the bottom plate and the top plate, and a second dielectric region, which extends between the first dielectric region and the contact region (42), the first and second dielectric regions being adjacent to one another. The second dielectric region has a surface (38a) having a plurality of grooves designed to increase the extension of a surface path between the second conductive layer (46) and the contact region (42).
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公开(公告)号：EP4024439A1
公开(公告)日：2022-07-06
申请号：EP21218230.7
申请日：2021-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： PATTI, Davide Giuseppe
IPC: H01L21/336 , H01L21/265 , H01L29/78
Abstract: A process is proposed for manufacturing an integrated device (100), which comprises at least one MOS transistor (105) integrated on a die (110) of semiconductor material. The process comprises forming one or more gate trenches (140) with corresponding field plates (160) and gate regions (155); a body region (130) is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface (125f) of the die (110). Moreover, a corresponding integrated device (100) and a system comprising this integrated device (100) are proposed.
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公开(公告)号：EP3151282B1
公开(公告)日：2020-11-11
申请号：EP16161888.9
申请日：2016-03-23
Applicant: STMICROELECTRONICS S.r.l.
Inventor： PATTI, Davide Giuseppe , GRIMALDI, Antonio Giuseppe
IPC: H01L29/08 , H01L29/78 , H01L21/336
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