公开(公告)号：KR1020100119409A

公开(公告)日：2010-11-09

申请号：KR1020090038511

申请日：2009-04-30

Applicant: 주식회사 실리콘웍스

Inventor： 김기덕 ,  조규형 ,  전용준 ,  전진용 ,  정승철 ,  이성우

IPC: H03M1/66 ,  H03M1/12

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/711 ,  H03M2201/814 ,  H03M2201/932

Abstract: PURPOSE: An apparatus for transferring a reference current is provided to reduce the size of an entire circuit by accurately sampling or holding the reference current regardless of the generation of mismatches in processes. CONSTITUTION: A first switch part(10) includes a first n-type metal oxide semiconductor(NMOS) transistor(11), a second NMOS transistor(13), and a third NMOS transistor(15). The first switch part transfers a reference current from reference current source(Ireft) according to a controlling signal. A sampling or holding part(20) includes a first current storing part(Cn) and a fourth NMOS transistor(21). The sampling or holding part samples or holds the reference current for a pre-set time. A second switch part(30) includes a first inverter(31) and a fifth NMOS transistor(33).

Abstract translation: 目的：提供用于传送参考电流的装置，以便通过精确地采样或保持参考电流来减小整个电路的尺寸，而不管工艺中产生不匹配。 构成：第一开关部件（10）包括第一n型金属氧化物半导体（NMOS）晶体管（11），第二NMOS晶体管（13）和第三NMOS晶体管（15）。 第一开关部分根据控制信号从参考电流源（Ireft）传送参考电流。 采样或保持部分（20）包括第一电流存储部分（Cn）和第四NMOS晶体管（21）。 采样或保持部分采样或保持参考电流达预设时间。 第二开关部分（30）包括第一反相器（31）和第五NMOS晶体管（33）。

公开(公告)号：KR1020080052270A

公开(公告)日：2008-06-11

申请号：KR1020070071103

申请日：2007-07-16

Applicant: 한국전자통신연구원

Inventor： 김이경 ,  김귀동 ,  권종기 ,  김종대

IPC: H03M3/02

CPC classification number: H03M3/39 ,  H03M3/37 ,  H03M2201/6309 ,  H03M2201/711

Abstract: A multi-bit delta sigma modulator is provided to be applied for a multi-bit high speed operation by delaying a feedback signal as much as one clock using a delayer and a differential delayer. A multi-bit delta sigma modulator includes a first integrator(301), a second integrator(303), an analog digital converter(305), a delayer(309), and a differential delayer(311). The first integrator integrates an input signal. The second integrator receives an input of the signal feedbacked from the differential delayer, and compensates for the delayed signal component. The analog digital converter converts the integrated signal into a digital signal. The delayer delays the signal outputted from the analog digital converter. The differential delayer differentiates and delays the signal outputted from the analog digital converter.

Abstract translation: 通过使用延迟器和差分延迟器延迟多达一个时钟的反馈信号，提供多位ΔΣ调制器用于多位高速操作。 多比特ΔΣ调制器包括第一积分器（301），第二积分器（303），模拟数字转换器（305），延迟器（309）和差分延迟器（311）。 第一个积分器集成了一个输入信号。 第二积分器接收从差分延迟器反馈的信号的输入，并补偿延迟的信号分量。 模拟数字转换器将集成信号转换为数字信号。 延迟器延迟模拟数字转换器输出的信号。 差分延迟器对从模拟数字转换器输出的信号进行微分和延迟。