公开(公告)号：US07573721B2

公开(公告)日：2009-08-11

申请号：US11749752

申请日：2007-05-17

Applicant: Ting-Hao Lin ,  Chien-Wei Chang

Inventor： Ting-Hao Lin ,  Chien-Wei Chang

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/108 ,  H05K3/205 ,  H05K2201/09236 ,  H05K2201/09881 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.

Abstract translation: 介绍了嵌入式无源器件结构及其主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部的多个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。

公开(公告)号：US10779405B2

公开(公告)日：2020-09-15

申请号：US16045236

申请日：2018-07-25

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

公开(公告)号：US10440837B2

公开(公告)日：2019-10-08

申请号：US15864754

申请日：2018-01-08

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

Abstract: A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

公开(公告)号：US10383265B2

公开(公告)日：2019-08-13

申请号：US16115119

申请日：2018-08-28

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. The EMI shielding device is adopted to be mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US20190160805A1

公开(公告)日：2019-05-30

申请号：US16199515

申请日：2018-11-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Shang-Chi WANG ,  Yun-Han YEH ,  Cyuan-Bang WU

IPC: B32B43/00

Abstract: A foil peeling apparatus adapted to a substrate having a foil thereon includes a foil peeling member, a connector and a controller. The foil peeling member has a foil peeling surface. The controller controls the connector to drive the peeling member to move along a path. The foil peeling surface of the peeling member in contact with, with an initial angle, the substrate, feeds toward the substrate for a first displacement, and then moves upwards and toward the substrate when the first feeding angle is decreased.

公开(公告)号：US09831167B1

公开(公告)日：2017-11-28

申请号：US15678130

申请日：2017-08-16

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Kuo-Chun Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/13 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/061 ,  H01L2924/00

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier board in order to form a compound carrier board structure. A die is placed in the opening and bonded to the carrier board. A sealant is filled in a gap between surrounding walls of the opening and the die at a height lower than the die to fixedly place the die within the opening and to leave a non-active surface of the die exposed.

公开(公告)号：US09754870B2

公开(公告)日：2017-09-05

申请号：US15071368

申请日：2016-03-16

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Kuo-Chun Huang

IPC: H01L23/498 ,  H01L23/31 ,  H05K3/46 ,  H01L23/00 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/061 ,  H01L2924/00

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening bonded to a non-conductive film then a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.

公开(公告)号：US09351409B2

公开(公告)日：2016-05-24

申请号：US13960123

申请日：2013-08-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Hsueh-Ping Chien ,  Jun-Chung Hsu

IPC: H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K3/22

CPC classification number: H05K3/4682 ,  H05K3/007 ,  H05K3/22 ,  H05K2201/2009 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/162

Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material layer on the support plate.

Abstract translation: 制造薄支撑包装结构的方法包括以下步骤：制备形成有与其外缘相邻的多个槽的支撑板，在支撑板上形成释放材料层; 在所述释放材料层上形成第一电路层以形成薄电路板; 在释放材料层上形成介电层; 在介电层中形成多个开口; 在所述电介质层上形成第二电路层; 通过填充开口形成连接插头; 在电介质层上形成焊料掩模; 在所述支撑板的下表面上分别形成多个凹槽以与所述凹槽连通; 并且在支撑板上的切口和释放材料层的中心部分之间移除支撑板的中心部分。

公开(公告)号：US20150282306A1

公开(公告)日：2015-10-01

申请号：US14225671

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4679 ,  H05K1/116 ,  H05K2201/0376

Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.

Abstract translation: 多层基板结构包括第一塑料片，第二塑料片，第一电路图案层，第二电路图案层和层间连接垫。 连接到层间连接焊盘的第一连接插头填充第一塑料片的第一开口并连接到第一电路图案层的第一连接焊盘。 第二连接插头填充第二塑料片的第二开口并且连接到第二电路图案层的第二连接焊盘，使得第二电路图案层经由层间连接焊盘电连接到第一电路图案层。 因此，即使几乎没有偏移，也可以克服对准公差，并且根据需要确保电路层之间的电连接。

公开(公告)号：US20150140262A1

公开(公告)日：2015-05-21

申请号：US14085033

申请日：2013-11-20

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Yu-Hsiang SUN ,  Jun-Chung HSU

IPC: H01B3/47 ,  H01B3/40

CPC classification number: H01B3/47 ,  H01B3/40 ,  H01B3/448 ,  Y10T428/24273

Abstract: An insulation layer structure includes an insulation layer, at least one glass fiber embedded in the insulation layer and at least one opening penetrating through the insulation layer and cutting off the glass fiber. The glass fiber projects from a sidewall of the opening such that the ratio of the length of the glass fiber projecting from the sidewall to the width of the opening is 0.2˜33%. With the glass fiber projecting from the sidewall of the opening, the sidewall of the opening has large surface roughness and the surface area to contact with the electrolyte. As a result, the crystal growth rate for the electrolyte onto the sidewall is accelerated. Therefore, the adhesion between the electroplating layer and the sidewall of the opening is increased, thereby improving the reliability and the yield rate of the product.

Abstract translation: 绝缘层结构包括绝缘层，至少一个嵌入绝缘层中的玻璃纤维和穿过绝缘层并切断玻璃纤维的至少一个开口。 玻璃纤维从开口的侧壁突出，使得从侧壁突出的玻璃纤维的长度与开口的宽度的比率为0.2〜33％。 当玻璃纤维从开口的侧壁突出时，开口的侧壁具有较大的表面粗糙度和与电解液接触的表面积。 结果，加速了电解质在侧壁上的晶体生长速度。 因此，提高了电镀层与开口侧壁的粘合性，提高了产品的可靠性和成品率。