公开(公告)号：US20150271915A1

公开(公告)日：2015-09-24

申请号：US14223661

申请日：2014-03-24

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Bo-Yu Tseng ,  Yu-Hsiang Sun

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K1/0206 ,  H05K1/0298 ,  H05K3/3436

Abstract: An enhanced chip board package structure includes a chip board and a plurality of enhanced structures, which are formed in the blind openings of the non-effective region of the chip board. Each enhanced structure has an opening. The mechanical strength is reinforced by the enhanced structures without changing the whole thickness so as to overcome the problem of warping. Meanwhile, the three-dimensional stability is thus enhanced. The opening of the enhanced structure can be selectively filled with the filler such that the mechanical strength is further reinforced and the thermally conductive effect is greatly improved.

Abstract translation: 增强的芯片板封装结构包括芯片板和多个增强结构，其形成在芯片板的非有效区域的盲孔中。 每个增强结构都有一个开口。 机械强度通过增强的结构增强，而不改变整个厚度，从而克服翘曲的问题。 同时，三维稳定性得到提高。 增强结构的开口可以选择性地填充填料，使得机械强度进一步增强，导热效果大大提高。

公开(公告)号：US20150041183A1

公开(公告)日：2015-02-12

申请号：US13960082

申请日：2013-08-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Yu-Hui Wu ,  Huei-Cheng Hong

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/09 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/0338 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A chip board package structure includes a circuit board part, a chip board part and a solder used to solder the circuit board part and the chip board part. A chip on the chip board part is connected to an electrical circuit by wiring or soldering. A surface treatment metal layer includes at least nickel, palladium and gold formed on part of the surface of the circuit layer on the chip board. A copper-tin intermetallic compound is formed on joints of the second solder and the surface treatment metal layer, and the other part of the circuit layer is directly connected to the solder to form the copper-tin intermetallic compound. In addition to the lower package cost, with the shape feature of the copper-tin intermetallic compound, it is possible to increase the contact area with the solder, thereby improving the reliability of the soldering process and the yield.

Abstract translation: 芯片组封装结构包括电路板部分，芯片板部分和用于焊接电路板部分和芯片板部分的焊料。 芯片部分的芯片通过布线或焊接连接到电路。 表面处理金属层至少包括在芯片板上的电路层表面的一部分上形成的镍，钯和金。 在第二焊料和表面处理金属层的接合部上形成铜锡金属间化合物，电路层的另一部分与焊锡直接连接，形成铜锡金属间化合物。 除了较低的封装成本之外，通过铜 - 锡金属间化合物的形状特征，可以增加与焊料的接触面积，从而提高焊接工艺的可靠性和产率。

公开(公告)号：US20150041205A1

公开(公告)日：2015-02-12

申请号：US13960159

申请日：2013-08-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Hsueh-Ping Chien ,  Jun-Chung Hsu

IPC: H05K1/11

CPC classification number: H05K1/0268 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/09472

Abstract: A thin package structure with enhanced strength includes a support carrier plate and a thin circuit board. The thin circuit board is formed on the support carrier plate and includes a first circuit layer, a dielectric layer and a second circuit layer. The first circuit layer includes the first circuit patterns and the first connection pads. The dielectric layer covers the first circuit layer. The second circuit layer is formed on or embedded in an upper surface of the dielectric layer and includes the second circuit patterns and the second connection pads. Connection plugs are formed in the dielectric layer to connect the first and second connection pads. The support carrier plate provides mechanical strength to avoid warping or deforming. It is feasible to direct test the package structure without disassembling so as to improve the convenience in testing.

Abstract translation: 具有增强强度的薄封装结构包括支撑载板和薄电路板。 薄板电路板形成在支承载板上，包括第一电路层，电介质层和第二电路层。 第一电路层包括第一电路图案和第一连接焊盘。 电介质层覆盖第一电路层。 第二电路层形成在电介质层的上表面上或嵌入在电介质层的上表面中，并且包括第二电路图案和第二连接焊盘。 在电介质层中形成连接插头以连接第一和第二连接焊盘。 支撑载体板提供机械强度以避免翘曲或变形。 在不拆卸的情况下直接测试包装结构是可行的，以提高测试的便利性。

公开(公告)号：US20130224513A1

公开(公告)日：2013-08-29

申请号：US13663141

申请日：2012-10-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H05K1/03

CPC classification number: H05K3/28 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0347

Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface overlaps the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.

Abstract translation: 公开了一种具有多层电路结构的叠层电路板，其包括基板，第一电路金属层，第二电路金属层，第一纳米镀层，第二纳米镀层和覆盖层。 第一电路金属层嵌入衬底中或形成在衬底的平滑的至少一个表面上。 具有平滑表面的第一纳米镀层与第一电路金属层重叠。 第二纳米镀层形成在基板的另一个表面上，并填满覆盖层中的开口以电连接第一电路金属层。 通过纳米电镀层和覆盖层/基板之间的化学键合来改善连接粘附。 因此，电路金属层不需要粗糙化，电路密度增加。

公开(公告)号：US08837808B2

公开(公告)日：2014-09-16

申请号：US13721015

申请日：2012-12-20

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Chia-Chi Lo ,  Cheng-Hsiung Yang ,  Jun-Chung Hsu

IPC: G06K9/00 ,  G06T7/00

CPC classification number: H05K1/0269 ,  H05K3/0008 ,  H05K3/225 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.

Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路​​板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。

公开(公告)号：US20140177939A1

公开(公告)日：2014-06-26

申请号：US13721015

申请日：2012-12-20

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chia-Chi Lo ,  Cheng-Hsiung Yang ,  Jun-Chung Hsu

IPC: G06T7/00

CPC classification number: H05K1/0269 ,  H05K3/0008 ,  H05K3/225 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.

Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路​​板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。

公开(公告)号：US20130219713A1

公开(公告)日：2013-08-29

申请号：US13663663

申请日：2012-10-30

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/24 ,  H05K3/4682 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49155

Abstract: A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented.

Abstract translation: 一种制造具有多层电路结构的叠层电路板的方法，包括以下步骤：在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成纳米电镀层，形成 盖层覆盖基板和纳米镀层，在盖层中形成孔，以产生露出纳米镀层的一部分的开口，最后在覆盖层上形成第二金属层以填充开口。 纳米电镀层用于通过化学键合获得与之前的粗糙化相同的效果，使得没有电路宽度被保留用于补偿，并且电路的密度增加，使得可以实现更加密集的电路。

公开(公告)号：US09351409B2

公开(公告)日：2016-05-24

申请号：US13960123

申请日：2013-08-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Hsueh-Ping Chien ,  Jun-Chung Hsu

IPC: H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K3/22

CPC classification number: H05K3/4682 ,  H05K3/007 ,  H05K3/22 ,  H05K2201/2009 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/162

Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material layer on the support plate.

Abstract translation: 制造薄支撑包装结构的方法包括以下步骤：制备形成有与其外缘相邻的多个槽的支撑板，在支撑板上形成释放材料层; 在所述释放材料层上形成第一电路层以形成薄电路板; 在释放材料层上形成介电层; 在介电层中形成多个开口; 在所述电介质层上形成第二电路层; 通过填充开口形成连接插头; 在电介质层上形成焊料掩模; 在所述支撑板的下表面上分别形成多个凹槽以与所述凹槽连通; 并且在支撑板上的切口和释放材料层的中心部分之间移除支撑板的中心部分。

公开(公告)号：US20150027756A1

公开(公告)日：2015-01-29

申请号：US13948274

申请日：2013-07-23

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Yu-Hui Wu

IPC: H05K1/02

CPC classification number: H05K1/0237 ,  H05K1/0242 ,  H05K2201/098

Abstract: A circuit board structure for high frequency signals includes a substrate and an electrical conductive circuit layer formed on the substrate. The conductive circuit layer includes circuit patterns and connection pads. The circuit pattern includes a base part with a shape of a rectangular block and a circular top part with a hemispherical shape provided on the base part. The circular top part can be modified by a circular bottom part embedded in the dielectric plastic film. Alternatively, a double layer structure with the circular top and bottom parts is formed such that the surface of the circuit pattern is provided with hemispheres to strengthen the reflection, thereby overcoming the problem of signal concentration due to the rectangular structure or the issue of signal attenuation due to surface roughness.

Abstract translation: 用于高频信号的电路板结构包括基板和形成在基板上的导电电路层。 导电电路层包括电路图案和连接焊盘。 电路图案包括具有矩形块形状的基部和设置在基部上的具有半球形状的圆顶部。 圆形顶部可以通过嵌入在介电塑料膜中的圆形底部部分进行修改。 或者，形成具有圆形顶部和底部的双层结构，使得电路图案的表面设置有半球以加强反射，从而克服由于矩形结构引起的信号集中或信号衰减的问题 由于表面粗糙度。

公开(公告)号：US08547548B1

公开(公告)日：2013-10-01

申请号：US13721019

申请日：2012-12-20

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Chia-Chi Lo ,  Cheng-Hsiung Yang Yang ,  Jun-Chung Hsu

IPC: G01N21/00

CPC classification number: G01N21/8803 ,  G01N2021/8861 ,  G01N2021/888

Abstract: Disclosed is a final defect inspection system, which including a host device, a microscope, a bar code scanner, a support tool, a signal transceiver and an electromagnetic pen. The bar code scanner scans a bar code on a circuit board provided on the support plate. The host device selects data and a circuit layout diagram from the database corresponding to the bar code. The signal transceiver and the electromagnetic pen are electrically connected to the host device. The electromagnetic pen is used to make a mark on a scrap region of the circuit board where any defect is visually found through the microscope. The signal transceiver receives and transmits the positions of the mark to the host device such that the host device calculates the coordinate of a scrap region based on a relative position between an original point and the positions of the mark.

Abstract translation: 公开了一种最终缺陷检查系统，其包括主机，显微镜，条形码扫描器，支持工具，信号收发器和电磁笔。 条形码扫描器扫描设置在支撑板上的电路板上的条形码。 主机设备从与条形码对应的数据库中选择数据和电路布局图。 信号收发器和电磁笔电连接到主机设备。 电磁笔用于在电路板的废料区域上形成标记，其中通过显微镜在视觉上发现任何缺陷。 信号收发器接收和发送标记的位置到主机设备，使得主机设备基于原始点和标记位置之间的相对位置来计算废料区域的坐标。