CIRCUIT FOR CONTROL OF MUTUAL EXCHANGE OF DATA BETWEEN LOCAL AREA NETWORK AND DATA BUS OF COMPUTER AND METHOD FOR AUTOMATIC RECONSTITUTION OF ABOVE CIRCUIT

    公开(公告)号:JPH0697944A

    公开(公告)日:1994-04-08

    申请号:JP13811393

    申请日:1993-06-10

    Abstract: PURPOSE: To select a port without the need for the user to set a switch and a jumper bus by allowing the circuit to be operated by the configuration of a 10-base-T specification, when it senses automatically that a 10-base-T port using a twisted wire pair is active and to select an AUI port using a coaxial medium, when the port is inactive. CONSTITUTION: A coaxial medium is connected to a LAN control circuit board 1 of a transceiver IC 60, via an attachment unit interface(AUI) connected to an AUI port 42. Media 47, 48 of the twisted wire pair are equipped with the board 1, via a 10-base-T port. Upon the receipt of a valid signal from the 10- base-T port by a link integrity state machine 35, the integrated circuit 60 provides an output of the signal to the twisted pairs 47, 48 from the 10-base-T port. When the signal from the 10-base-T port is not valid, the integrated circuit 60 provides an output of the signal to a coaxial medium from the AUI port 42. A transmission circuit for a 10-base 2, a 10-base 5 or a 10-base-T is automatically reconfigured.

    METHOD FOR FORMATION OF MULTILAYER LEAD- FRAME ASSEMBLY AND DIE PACKAGE OF MULTILAYER INTEGRATED CIRCUIT

    公开(公告)号:JPH0685157A

    公开(公告)日:1994-03-25

    申请号:JP493793

    申请日:1993-01-14

    Abstract: PURPOSE: To make it possible to manufacture a multilayered lead frame assembly for an integrated circuit die package, by a method wherein more than one insulating tape and a plane metal member are bonded together as the multilayered lead frame assembly. CONSTITUTION: B stage adhesion layers 20 and 40 are previously selected so that they are curable at different temperatures for enabling to bond separately a plane metal lead frame and a metal member operable as a ground plane and a heat sink to the opposed surfaces of an insulating tape 30. For example, it is possible that the layer 20 is curable at a temperature of 175 deg.C, but on the other hand, it is possible that the layer 40 is curable at a temperature of 275 deg.C. As the result, the B stage layers are used for bonding the lead frame to the tape 30 at a temperature which does not cure the layer 40, and subsequently to it, it is made possible that the metal member is separately bonded to the surface on one side of the opposed surfaces of the tape 30 afterwards.

    MASTER/SLAVE INSPECTION SYSTEM
    93.
    发明专利

    公开(公告)号:JPH0683658A

    公开(公告)日:1994-03-25

    申请号:JP13893491

    申请日:1991-06-11

    Abstract: PURPOSE: To execute the function of an inspection system without preventing the normal execution of a program by a master/slave constitution. CONSTITUTION: A slave 12 receives the input and output of a master 10, generates an output imitating the operation of the master 10 based on the input, compares the imitating output with the output of the master 10, and indicates an error state 20 when both are not equal. An inspection device 30 forcedly prepares a difference between the imitating output and the output of the master 10, and inspects whether or not the presence of the forced error is correctly judged by the master/slave constitution.

    DEVICE AND METHOD FOR GENERATING INTERRUPTION

    公开(公告)号:JPH0675779A

    公开(公告)日:1994-03-18

    申请号:JP15236693

    申请日:1993-06-23

    Abstract: PURPOSE: To enable and disable interruption by a software by providing a structure for indicating software and hardware situations, and a structure for generating interruption when the assertion of an interruption request signal is generated. CONSTITUTION: When a processor is turned into an idle mode, an IDLE INDICA TOR CIRCUIT 22 asserts an IDLE signal on a line 24, the output of an OR gate 28 is turned to a high level, and as long as the level is held, a latch 10 is set by the assertion of an interruption request signal INTO on a line 4, and interruption is generated. Then, while the processor is in the IDLE mode, an interruption flag IEO is set by the assertion of the interruption request signal INTO, and even when the interruption is masked by software, it is recognized by the processor. Also, when the processor is not in the idle mode, the IDLE signal on the line 24 is remaining in a low level, and the possibility and impossibility of the interruption is decided by a SOFTWARE ENABLE signal on a line 26.

    METHOD AND APPARATUS FOR FORMING COVARIANCE MATRIX

    公开(公告)号:JPH0660106A

    公开(公告)日:1994-03-04

    申请号:JP14372193

    申请日:1993-06-15

    Abstract: PURPOSE: To provide the device and method to generate a covariance matrix. CONSTITUTION: The device from a standpoint of one aspect is made up of in general, memories 12, 48, a ring buffer, a multiplier accumulator 32, and an arithmetic logic device. The memory includes plural sample representatives of an array and the ring buffer is configured to provide memory locations of a prescribed number. As the generating method of the covariance, the architecture above is in use and the covariance matrix based on the values is efficiently generated in the memories. In the method from a standpoint of one aspect, all the memories 12, 48, the ring buffer, the multiplier accumulator 32, and the arithmetic logic device are operated in parallel and the resource provided by the architecture is sufficiently utilized.

    KEY PAD MONITOR
    97.
    发明专利

    公开(公告)号:JPH0643989A

    公开(公告)日:1994-02-18

    申请号:JP19012291

    申请日:1991-07-30

    Abstract: PURPOSE: To effectively use an input terminal pin by detecting the state of a key pad switch with the set of monitor input terminals, which correspond to a selected mode. CONSTITUTION: When a system operates in a first operation mode, row input terminal pins 60-68 are connected to row conductors 160-168. Column input terminal pins 70-78 are connected to row conductors 170-178. In such a case the key pad monitor of a telephone set 12 can support the key pad 26 having 25 key pad switches. At a second operation mode, the row input terminal pins 60-64 are connected to the row conductors 160-164 and the column input terminal pins 70-74 are connected to the row conductors 170-174. In such a case, nine key pad switches are supported. The remaining pins are used for a purpose except for the monitoring of the key pad 26.

    METHOD AND APPARATUS FOR USAGE OF 8-BIT- WIDTH BUFFER MEMORY ON 8-BIT-WIDTH LOCAL BUS, FOR HIGH-SPEED READOUT, INTERFACED WITH ISA BUS IN 16-BIT-WIDTH MODE

    公开(公告)号:JPH0628309A

    公开(公告)日:1994-02-04

    申请号:JP10437993

    申请日:1993-04-30

    Abstract: PURPOSE: To reduce the cost of the buffer memory of a peripheral device by using prefetch and giving prefetched data to a bus at the time when the next memory address matches with a forecasted memory address. CONSTITUTION: A local data bus is converted from 16-bit width to 8-bit width, and a single 8-bit width DRAM chip 10 and a PROM chip 11 are used. A local memory read sequence is executed in response to a memory read command from an ISA bus including a memory fetch address, and the memory fetch address matches the forecasted next address. The forecasted next address is incrementation of the next but one memory fetch address derived from the ISA bus. In response to suggestion of matching, data derived from the forecasted next address position is immediately presented to an ISA system data bus. This operation is completed in a minimum access time of ISA bus specifications.

    INTEGRATED DIGITAL DEVICE FOR USE IN COMPUTATION APPARATUS

    公开(公告)号:JPH05314062A

    公开(公告)日:1993-11-26

    申请号:JP21731791

    申请日:1991-08-28

    Abstract: PURPOSE: To provide a digital processor which is constituted as an integrated circuit on a single substrate for housing a plurality of peripheral buses. CONSTITUTION: A device 10 positioned on a single substrate 12 contains a computer processor 14, a connection 16 for S-bus, and a supporting peripheral device 18 incorporated with an S-bus interface circuit 20, and a bus master supporting circuit 22. A connection 24 for M-bus is related to a dynamic random access memory (RAM) controller 28, a random access memory (RAM), an M-bus supporting peripheral device 26 containing a controller 30. An S-bus supporting peripheral device 34 is correlated with an X-bus connection 32 and contains an X-bus interface 36.

Patent Agency Ranking