公开(公告)号：EP1811653A1

公开(公告)日：2007-07-25

申请号：EP06100662.3

申请日：2006-01-20

Applicant: STMicroelectronics SA ,  STMicroelectronics Design and Application S.R.O.

Inventor： Saman, Hynek ,  Murin, Peter ,  Boksa, Martin ,  Panus, Pavel

IPC: H03F1/30 ,  H03F3/217 ,  H03F3/72 ,  G05F1/575

CPC classification number: H03F1/30 ,  H03F1/26 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/72 ,  H03F2200/372 ,  H03F2200/459 ,  H03F2203/45534

Abstract: The invention concerns a switch comprising a first transistor comprising a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage level, and first control means connected to said control terminal of said first transistor, comprising a first node connected to said first clean voltage level, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, said first control means arranged to selectively connect said control terminal of said first transistor to one of said first node and said second node based on said first input control signal.

Abstract translation: 本发明涉及一种包括第一晶体管的开关，第一晶体管包括连接到第一开关节点的第一主端子，连接到第二开关节点的第二主端子和控制端子，第二开关节点连接到第一清洁电压电平，以及 连接到所述第一晶体管的所述控制端的第一控制装置，包括连接到所述第一清洁电压电平的第一节点，连接到第二电压电平的第二节点和用于接收第一输入控制信号变量的控制输入节点 电源电压和第三电压电平，所述第一控制装置被布置成基于所述第一输入控制信号选择性地将所述第一晶体管的控制端连接到所述第一节点和所述第二节点之一。

公开(公告)号：EP4137954A1

公开(公告)日：2023-02-22

申请号：EP22188131.1

申请日：2022-08-01

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： DVORAK, Vaclav ,  RENNIG, Fred

IPC: G06F13/42 ,  G06F12/0806 ,  G06F13/40 ,  H04L12/40 ,  G06F13/28 ,  G06F13/38

Abstract: A processing system (10a) is described. The processing system comprises a Serial Peripheral Interface, SPI, communication interface (50), a microprocessor (1020), a memory controller (100) connected to a memory (104, 104b), and two DMA channels (DMA 1 , DMA 2 ) configured to transfer packets between the SPI interface (50) and the memory (104b). In particular, the processing system comprises an edge detector (600, 620) configured to assert a first control signal (IRQ 60 ) in response to a falling edge in the reception signal (RXD), a first hardware timer circuit (60) configure to, when enabled, generate a clock signal (PWM) for the SPI communication interface (50) and a second hardware timer circuit (62) configure to, when enabled, increase a count value and assert a second control signal (IRQ 62 ) in response to determining that the count value reaches a given threshold value.
Specifically, the processing system (10a) is configured to manage a CAN FD Light data transmission mode and/or CAN FD Light data reception mode by using the SPI communication interface. For example, in the CAN FD Light data reception mode, the microprocessor (1020) activates a slave mode of the SPI communication interface (50), enables the first hardware timer circuit (60) and the second hardware timer circuit (62) in response to the first control signal (IRQ 60 ), whereby the second DMA channel (DMA 2 ) transfers packets from the SPI communication interface (50) to the memory (104b), thereby sequentially transferring a reception CAN FD Light frame from the SPI communication interface (50) to the memory (104b), and reads the reception CAN FD Light frame from the memory (104b) in response to the second control signal (IRQ 62 ).

公开(公告)号：EP4057574A1

公开(公告)日：2022-09-14

申请号：EP22157917.0

申请日：2022-02-22

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： RENNIG, Fred ,  DVORAK, Vaclav

IPC: H04L12/40 ,  H03K7/08

Abstract: A circuit (106) comprises a first (24a) and a second (24b) memory, a processing unit (21) and a timer (22). The processing unit generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. Each PWM period has a dominant portion and a recessive portion, and a total duration. The processing unit stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory, wherein the first and second parameter define a shape of the PWM periods. The timer comprises a first register (220) which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter (221) which increases a count number and resets the count number as a function of the value of the first register. A value of the first parameter of a subsequent PWM period is stored into the first register as a function of the value of the first register. The timer comprises a second register (222) which reads from the second memory a value of the second parameter of the current PWM period, and compares the count number of the counter circuit to such value. The second register drives an output pin (230) to a dominant (resp., recessive) value as a function of said comparing the count number of the counter circuit to the value of the second register. A value of the second parameter of a subsequent PWM period is stored into the second register in response to the count number reaching the value stored in the first or second register.

公开(公告)号：EP3913767A1

公开(公告)日：2021-11-24

申请号：EP21172661.7

申请日：2021-05-07

Applicant: STMicroelectronics Design and Application s.r.o.

Inventor： TOULA, Mr. Michal

IPC: H02J50/12 ,  H02H9/04

Abstract: A wireless charging receiver (500) includes a controller (310) configured to determine that a first overvoltage threshold is met and based thereon enable a first switch (510) to couple an output of a rectifier (314) to electrical ground through a first resistor (510), to determine that a second overvoltage threshold is met and based thereon enable receive resonant circuit switches (515) to short circuit a receive resonant circuit (335), to determine that a hysteresis threshold is met and based thereon disable the receive resonant circuit switches (515) to open circuit the receive resonant circuit (335) , and to determine that a hysteresis cycle threshold is met and that the receive resonant circuit switches (515) are disabled and based thereon enable a second switch (525) to couple a second resistor (520) to the electrical ground and to communicate to wireless charging transmitter to decrease the power level on wireless charging receiver side.

公开(公告)号：EP3885924A1

公开(公告)日：2021-09-29

申请号：EP21162262.6

申请日：2021-03-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： NANDLINGER, Mr. Rolf ,  OLEXA, Mr. Radek

IPC: G06F13/40

Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

公开(公告)号：EP3330829A1

公开(公告)日：2018-06-06

申请号：EP17176566.2

申请日：2017-06-19

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics Asia Pacific Pte Ltd.

Inventor： PROCHAZKA, Roman ,  CHEONG, Chee Weng

IPC: G05F3/26

Abstract: A current mirror circuit includes an input current leg (112) and an output current leg (114). The input current leg includes: a first bipolar junction transistor (BJT) (120) having a collector terminal configured to receive an input current sourced at a current node (104) and a first metal oxide semiconductor field effect transistor (MOSFET) (102) having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the first BJT (120). The output current leg (114) includes: a second BJT (122) having a collector terminal configured to supply an output current and a second MOSFET (106) having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the second BJT.

公开(公告)号：EP2587335A3

公开(公告)日：2013-09-04

申请号：EP12199540.1

申请日：2009-12-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Design and Application S.R.O.

Inventor： Loidl, Ales ,  Bellomo, Ignazio ,  Giussani, Luca ,  Vincenzoni, David

IPC: G06F1/02

CPC classification number: G06F1/025

Abstract: A state machine for generating signals configured for generating different signals according to the current state (SO, S1, S2, S3, IDLE) of the machine. The state machine is configured to change state both as a function of an internal timer (Cmp(n)) and as a function of signals (Edge(x); Edge (y)) representative of events external to the state machine.

公开(公告)号：EP2339424A1

公开(公告)日：2011-06-29

申请号：EP10196632.3

申请日：2010-12-22

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Petenyi, Sandor

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: An electronic integrated device (100) comprises a signal generation stage (101) arranged to generate a first signal (UVLO) representative of an under voltage lockout logic signal, said signal generation stage comprising a voltage divider block (102) arranged to provide an internal reference voltage signal (VBGI) to a bandgap core group (104) on the basis of a reference signal (VDD), said bandgap core group (104) generating said first signal (UVLO) on the basis of said internal reference voltage signal (VBGI). The bandgap core group (104) further comprises a first generation module (105) arranged to generate a output regulated reference voltage signal (OVBG) on the basis of said internal reference voltage signal, and a second generation module (108) arranged to generate said first signal (UVLO) on the basis of said internal reference voltage signal (VBGI) and a driving signal (ds) obtained by a preliminary processing of said internal reference voltage signal (VBGI) by a bandgap core module (106) included within said band gap core group (104).

Abstract translation: 一种电子集成器件（100）包括被设置成产生第一信号（UVLO）代表一个欠压锁定逻辑信号，所述信号发生级包括布置成提供到内部分压器块（102）的信号发生级（101） 参考电压信号（VBGI）的参考信号（VDD）的基础上的带隙芯组（104），所述带隙芯组（104）产生所述第一信号（UVLO）所述内部基准电压信号的基础上（VBGI ）。 带隙芯组（104）还包括被设置成产生所述内部基准电压信号的基础上，一个输出调节的基准电压信号（OVBG）第一生成模块（105），并布置成产生所述的第二生成模块（108） 第一信号和所述内部基准电压信号（VBGI）和由带隙芯模块（106）通过（VBGI）所述内部基准电压信号的初步处理而获得的驱动信号（DS）的基础上（UVLO）包括在所述带内 间隙芯组（104）。

公开(公告)号：EP2075915A1

公开(公告)日：2009-07-01

申请号：EP07150488.0

申请日：2007-12-29

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Vacula, Patrik ,  Vacula, Milos ,  Lzicar, Milan

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1735 ,  H03K19/17796

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract translation: 集成掩模可编程装置，具有多个金属层，包括形成在顶部和底部金属层之间的顶部金属层，底部金属层和第一中间金属层，以及布置在底部和底部金属层之间的多个通孔层 中间金属水平和第一中间和顶部金属水平之间并且将每个金属水平连接到相邻的金属水平。 多个金属层形成第一，第二和至少第三末端，顶部和底部金属层具有至少两个金属区域，并且第一中间金属层具有至少三个金属区域。 第一端子连接到第三端子，或者通过修改单个金属或通孔电平将第二端子连接到第三端子。

公开(公告)号：EP4152171A1

公开(公告)日：2023-03-22

申请号：EP22206499.0

申请日：2021-03-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： NANDLINGER, Rolf ,  OLEXA, Radek

IPC: G06F13/40

Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).