Abstract:
A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.
Abstract:
An image sensor has an array of pixels each of which comprises a photodiode (P) in circuit with a semiconductor device (M2) to define a node (pix). The pixel can be operated in linear mode with reset voltage (Vrt) applied via device M4. The pixel can also be operated in logarithmic mode by asserting 'logsel' to enable device M2 to conduct the photocurrent. In logarithmic mode, means are provided for calibrating the pixels to remove fixed pattern noise. The pixels may be operated in linear and log modes sequentially, with the linear output being selected for low light signals and the log output being selected for high light signals.
Abstract:
A port protection circuit, in particular for protecting a JTAG port, comprises logic gates which are switchable to allow the JTAG port to access scan chains or a Diagnostic Control Unit (DCU). The gating arrangement is controlled by a protection circuit that requires a private key to be input through the JTAG port to "unlock" a circuit so that the gating components allow connection between the JTAG port and scan chains or the DCU.
Abstract:
A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.
Abstract:
A solid state image sensor has an array of pixels formed on an epitaxial layer (10) on a substrate (12). The pixel is large, 40-60 µm, for high light collecting ability, but the pixel photodiode (14') is small, 4-6 µm, for low capacitance. Active elements of the pixel are formed in wells (16) which are spaced away from the photodiode (14') so that the latter is surrounded by epitaxial material.
Abstract:
An image sensor has an array of pixels (10). Each column has a first (16) and a second (20) column line connected to a read-reset amplifier/comparator (22) which acts in a first mode as a unity gain buffer amplifier to reset the pixels (10) via the first lines (16), and in a second mode acts as a comparator and AD converter to produce digitised reset and signal values. The reset and signal values are read out a line at a time in interleaved fashion. Reset values are stored in a memory (26) and subsequently subtracted from the corresponding signal values. The arrangement reduces both fixed pattern and kT/C noise.
Abstract:
An image sensor has pixels of four-transistor, pinned-photodiode type. In each pixel, the charge on a photodiode (22) is transferred by transfer gate (14) to a sensing node (Vpix). Readout of reset and read voltages is via an amplifier (36). A gain capacitor (Ch) is connected in feedback across the amplifier (36) and the read and reset gates are controlled such that the pixel is reset to a virtual ground voltage controlled by Ch and independent of the pixel parasitic capacitance (Cp).
Abstract:
A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.