公开(公告)号：KR100295058B1

公开(公告)日：2001-07-12

申请号：KR1019990018861

申请日：1999-05-25

Applicant: 삼성전자주식회사

Inventor： 김형섭 ,  유재윤 ,  구자흠

IPC: H01L21/334

Abstract: 액상증착(liquid phase deposition)을이용한반도체장치의게이트구조제조방법을개시한다. 본발명의일 관점은, 반도체기판상에실리콘막을형성한다. 실리콘막상에포토레지스트패턴을형성한다. 포토레지스트패턴을식각마스크로이용하여실리콘막을패터닝하여실리콘패턴을형성한다. 실리콘패턴에의해서노출되는반도체기판상에포토레지스트패턴과의선택특성을이용하여포토레지스트패턴의상부표면을노출하는실리콘산화막을액상증착으로선택적으로형성한다. 포토레지스트패턴을제거한다. 포토레지스트패턴의제거에의해서노출되는실리콘패턴상에실리콘산화막간의갭을채우는코발트실리사이드패턴을형성한다. 실리콘산화막을제거하여코발트실리사이드패턴및 실리콘패턴으로이루어지는게이트구조를형성한다.

公开(公告)号：KR1020010055887A

公开(公告)日：2001-07-04

申请号：KR1019990057210

申请日：1999-12-13

Applicant: 삼성전자주식회사

Inventor： 김철성 ,  구자흠 ,  최철준

IPC: H01L21/336

Abstract: PURPOSE: A method for forming a gate line of a semiconductor device by using a dichlorosilane tungsten silicide layer is provided to increase a drive current of a transistor by improving interface characteristics of a gate insulating layer. CONSTITUTION: In the method, the gate insulating layer(42) is formed on a substrate(40), and then a polysilicon layer(44) is formed on the gate insulating layer(42). Next, fluorine is implanted into the polysilicon layer(44), and then the dichlorosilane tungsten silicide layer(48) is formed on the polysilicon layer(44). The implantation of fluorine may be performed after the formation of the silicide layer(48). Next, by a following heat treatment, fluorine implanted in the polysilicon layer(44) and also produced during the formation of the silicide layer(48) is diffused into the gate insulating layer(42), and thereby silicon-oxygen bonds are partly broken in the gate insulating layer(42) and instead silicon-fluorine bonds are newly formed. In addition, oxygen separated from the silicon-oxygen bonds is moved to upper and lower interfaces of the gate insulating layer(42) and therefore forms a defect-free silicon-oxygen bond layer(50) improving interface characteristics of the gate insulating layer(42).

Abstract translation: 目的：提供通过使用二氯硅烷硅化钨层形成半导体器件的栅极线的方法，通过改善栅极绝缘层的界面特性来增加晶体管的驱动电流。 构成：在该方法中，栅极绝缘层（42）形成在基板（40）上，然后在栅极绝缘层（42）上形成多晶硅层（44）。 接着，将氟注入到多晶硅层（44）中，然后在多晶硅层（44）上形成二氯硅烷硅化钨层（48）。 可以在形成硅化物层（48）之后进行氟的注入。 接下来，通过后续的热处理，注入到多晶硅层（44）中并且在形成硅化物层（48）期间产生的氟被扩散到栅极绝缘层（42）中，由此硅 - 氧键部分断裂 在栅极绝缘层（42）中，而是新形成硅 - 氟键。 此外，从硅 - 氧键分离的氧被移动到栅极绝缘层（42）的上部和下部界面，因此形成无缺陷的硅 - 氧键合层（50），改善栅极绝缘层的界面特性（ 42）。

公开(公告)号：KR1020000074817A

公开(公告)日：2000-12-15

申请号：KR1019990019025

申请日：1999-05-26

Applicant: 삼성전자주식회사

Inventor： 최철준 ,  구자흠 ,  김철성

IPC: H01L21/76

Abstract: PURPOSE: A trench isolation method using a porous silicon layer is provided to easily perform a process without deteriorating an isolation characteristic, by maintaining a depth of a real trench isolation while reducing the depth of the trench. CONSTITUTION: A trench is formed in a non active region of a semiconductor substrate(10). A spacer(18) is formed on an inner wall of the trench. A porous silicon layer is formed on a bottom surface of the trench. The porous silicon layer is oxidized. The trench is filled up with an insulating material. Also, after the porous silicon layer is oxidized, the oxidized porous silicon layer can be further densified.

Abstract translation: 目的：提供使用多孔硅层的沟槽隔离方法，以便通过在减小沟槽的深度的同时保持实际沟槽隔离的深度来容易地执行不劣化隔离特性的工艺。 构成：在半导体衬底（10）的非有源区中形成沟槽。 间隔物（18）形成在沟槽的内壁上。 在沟槽的底表面上形成多孔硅层。 多孔硅层被氧化。 沟槽填充有绝缘材料。 此外，在多孔硅层被氧化之后，氧化的多孔硅层可以进一步致密化。

公开(公告)号：KR1020000055922A

公开(公告)日：2000-09-15

申请号：KR1019990004830

申请日：1999-02-11

Applicant: 삼성전자주식회사

Inventor： 김철성 ,  구자흠 ,  이응준

IPC: H01L21/335

Abstract: PURPOSE: Metal silicide film forming method of semiconductor device provides to improve surface morphology and leakage characteristics. CONSTITUTION: Metal silicide film forming method of semiconductor device comprising a metal film(13) for silicide is formed on a silicone substrate(1) formed a transistor comprising a source(9), drainage(11), gate oxide film, gate electrode(5) and spacer(7), the silicone substrate(1) formed the metal film(13) performing Siliciding reaction firstly without generating bridge between the gate electrode(5) and the source(9) and drainage(11) by heat treating at 1st temperature of nitrogen or argon atmosphere. a high resistance metal silicide film(15) is formed on the source(9), the drainage(11), the gate electrode(5), as a high resistance metal silicide film(15), a CoSi is formed when, metal film is formed with Co. then non reacted material of metal film is removed generating when heat treated on the 1st temperature. The silicone substrate(1) which formed the high resistance metal silicide film(15) is performed a 2nd Siliciding process in the silicone source, as silane or disilane gas atmosphere with a higher temperature of 2nd temperature than the 1st temperature. then low resistance metal silicide film(17) is formed on the source(9),the drainage(11), the gate electrode(5).

Abstract translation: 目的：半导体器件的金属硅化物膜形成方法提供了改善表面形貌和漏电特性。 构成：包含用于硅化物的金属膜（13）的半导体器件的金属硅化物膜形成方法形成在形成晶体管的硅树脂衬底（1）上，所述硅树脂包括源（9），引流（11），栅极氧化膜，栅极电极 5）和间隔物（7），硅基底（1）首先形成进行硅化反应的金属膜（13），而不会在栅电极（5）和源（9）之间产生桥接，并通过热处理 第一温度为氮气或氩气氛。 在源（9），排水（11），栅电极（5）上形成作为高电阻金属硅化物膜（15）的高电阻金属硅化物膜（15），当金属膜 与Co形成，然后在第一温度下进行热处理时除去金属膜的非反应材料。 形成高电阻金属硅化物膜（15）的有机硅基板（1）在硅酮源中进行第二硅化工艺，作为具有比第一温度高的第二温度的硅烷或乙硅烷气体气氛。 然后在源极（9），引流（11），栅电极（5）上形成低电阻金属硅化物膜（17）。

公开(公告)号：KR1019990024819A

公开(公告)日：1999-04-06

申请号：KR1019970046185

申请日：1997-09-08

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  김병준 ,  윤여철 ,  최길현

IPC: H01L21/28

Abstract: 본 발명은 실리사이드층을 이용한 금속배선을 형성하는 방법에 관해 개시한다. 본 발명은 금속배선으로 사용되는 텅스텐층과 코발트 실리사이드층 사이에 형성되는 부착층을 상기 금속배선이 형성되기 전에 750℃∼850℃정도의 온도 범위에서 RTP처리하여 입자의 침투에 대한 내성을 높인다. 동시에, 상기 코발트 실리사이드층의 결정구조를 비저항이 낮은 결정구조로 변형한다. 이 결과, 상기 텅스텐층을 형성하는 과정에서 발생되는 불소가스(F)가 상기 장벽층을 투과하는 것을 방지하여 상기 불소가스에 의해 상기 코발트 실리사이드층이 손상되는 것을 방지함으로써 상기 텅스텐층과 코발트 실리사이드층 사이의 접촉저항을 낮게 유지할 수 있다.

公开(公告)号：KR102217246B1

公开(公告)日：2021-02-18

申请号：KR1020140157335

申请日：2014-11-12

Applicant: 삼성전자주식회사

Inventor： 박홍배 ,  구자흠 ,  김명철 ,  이진욱 ,  한성기

IPC: H01L29/78 ,  H01L21/336

Abstract: 집적회로소자는기판상에복수의활성영역과교차하는방향으로일 직선상에서연장되고상호이격되어있는제1 게이트라인및 제2 게이트라인과, 제1 게이트절연막및 제2 게이트절연막과, 제1 게이트라인과제2 게이트라인과의사이에개재되고제1 단축방향측벽및 제2 단축방향측벽에각각접하는게이트간절연영역을포함한다. 집적회로소자를제조하기위하여, 복수의활성영역중 더미게이트라인의양 측에서노출되는부분에한 쌍의소스/드레인영역을형성한후, 더미게이트라인을제거하여게이트홀을형성한다. 게이트홀 내에게이트절연막및 게이트층을형성한후, 게이트층중 일부를제거하여복수의게이트라인으로분리한다.

公开(公告)号：KR1020120108923A

公开(公告)日：2012-10-05

申请号：KR1020120013378

申请日：2012-02-09

Applicant: 삼성전자주식회사 ,  인터내셔널 비즈니스 머신즈 코오퍼레이션

Inventor： 김병동 ,  구자흠 ,  쉐퍼드조셉에프 ,  데쉬판드사다난드브이

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/205

CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: PURPOSE: A gate oxide film including a nitride film deposited thereon and a method for forming the gate oxide film are provided to prevent components of a high-K directive film from diffusing into an oxide film by forming a high density nitrogen blocking layer distributed at the top of the oxide film. CONSTITUTION: A gate oxide film(20) is formed on a channel region of a semiconductor substrate(10). A nitride film is deposited on the gate oxide film. The deposited nitride film is oxidized to form a barrier layer. A high-K dielectric film(30) is deposited on the oxidized nitride film. A metal gate(40) is formed on the high-K dielectric film.

Abstract translation: 目的：提供一种包括沉积在其上的氮化物膜的栅极氧化膜和形成栅极氧化膜的方法，以通过形成分布在该氧化膜上的高密度氮阻挡层来防止高K指向膜的成分扩散到氧化膜中 氧化膜顶部。 构成：在半导体衬底（10）的沟道区上形成栅极氧化膜（20）。 在栅极氧化膜上沉积氮化物膜。 沉积的氮化物膜被氧化以形成阻挡层。 在氧化氮化物膜上沉积高K电介质膜（30）。 在高K电介质膜上形成金属栅极（40）。

公开(公告)号：KR1020090007522A

公开(公告)日：2009-01-19

申请号：KR1020080006771

申请日：2008-01-22

Applicant: 삼성전자주식회사 ,  인터내셔널 비즈니스 머신즈 코오퍼레이션

Inventor： 이경우 ,  구자흠 ,  김전중 ,  선민철 ,  양종호 ,  장종광 ,  다이어,토마스어.

IPC: H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device manufacturing method is provided to remove a side space from a gate structure by using two spacer insulating layers each having different etching selection ratio, thereby preventing combination mechanism of a metal silicide structure. A conformal insulating layer(130') is formed on an active silicon region and a gate structure (111,121). While a part of the conformal insulating layer formed in a top surface and an upper sidewall of the gate structure is exposed, an etching mask of organic material covering a part of the conformal insulating layer formed on the active silicon region is formed. By using the etching mask of the organic material, the exposed part of the conformal insulating layer is etched. The surface of the active silicon region and the sidewall surface of the gate electrode are protected from etching damage while etching a second spacer insulating layer. Through an etching process where an etching selection ratio of material forming the second spacer insulating layer is bigger than an etching selection ratio of material forming the conformal insulating layer and a first spacer insulating layer(14), a second side wall spacer insulating layer of the first and second side wall spacers is removed. The first spacer insulating layer is comprised of oxide. The second spacer insulating layer is comprised of nitride.

Abstract translation: 提供半导体器件制造方法，通过使用具有不同蚀刻选择比的两个间隔绝缘层从栅极结构去除侧面空间，从而防止金属硅化物结构的组合机制。 在活性硅区域和栅极结构（111,121）上形成保形绝缘层（130'）。 虽然形成在栅极结构的顶表面和上侧壁中的保形绝缘层的一部分被暴露，但是形成覆盖形成在有源硅区上的共形绝缘层的一部分的有机材料的蚀刻掩模。 通过使用有机材料的蚀刻掩模，蚀刻保形绝缘层的暴露部分。 在蚀刻第二间隔绝缘层的同时，保护活性硅区域的表面和栅电极的侧壁表面免受蚀刻损伤。 通过蚀刻工艺，其中形成第二间隔绝缘层的材料的蚀刻选择比大于形成保形绝缘层的材料的蚀刻选择比和第一间隔绝缘层（14），第二侧壁间隔绝缘层 去除第一和第二侧壁间隔物。 第一间隔绝缘层由氧化物构成。 第二间隔绝缘层由氮化物构成。

公开(公告)号：KR1020080093293A

公开(公告)日：2008-10-21

申请号：KR1020070037053

申请日：2007-04-16

Applicant: 삼성전자주식회사

Inventor： 장대진 ,  김형수 ,  구자흠 ,  심중현 ,  유영호

IPC: G02F1/13 ,  G02F1/13357

CPC classification number: H01J9/006

Abstract: A lamp assembling apparatus and a lamp assembling method using the same are provided to assemble a lamp automatically and simply even when a pitch between lamps is changed, thereby reducing manufacturing time and costs. A lamp arrangement unit(200) includes a mount stage(240) where plural lamps are arranged to be mounted. A lamp pressing unit(300,400) includes a gripper(310), a body pressing unit(340) and a lead pressing unit(430). The gripper holds and moves the lamp from the mount stage. The body pressing unit mounts a body of the lamp in a receiving vessel. The lead pressing unit mounts a lead of the lamp in the receiving vessel.

Abstract translation: 提供一种灯组装装置和使用其的灯组装方法，即使在灯之间的间距变化时也能够自动简单地组装灯，从而减少制造时间和成本。 灯配置单元（200）包括其中安装有多个灯的安装台（240）。 灯压单元（300,400）包括夹持器（310），主体按压单元（340）和引线按压单元（430）。 夹具保持并从安装台移动灯。 身体按压单元将灯体安装在接收容器中。 铅压单元将灯的引线安装在接收容器中。

公开(公告)号：KR1020080087612A

公开(公告)日：2008-10-01

申请号：KR1020070045458

申请日：2007-05-10

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  구자흠 ,  박재언

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an integrated circuit device, a method for manufacturing a semiconductor device, and a semiconductor device manufactured thereby are provided to form stably a contact plug in an inside of a contact hole formed on an upper surface of a silicide layer or in the silicide layer. A first, second, and third transistors are formed on a semiconductor substrate(100). The first and second transistors are covered with a first electrical insulating layer having a high internal stress characteristic to apply tensile stress or compressive stress to a channel region of the first transistor. The second and third transistors are covered with a second electrical insulating layer having a high internal stress characteristic to apply tensile stress or compressive stress to a channel region of the third transistor. A first opening is defined by the second electrical insulating layer by removing selectively a first region of the second electrical insulating layer to be extended in a gate electrode side of the second transistor. A first opening extended through the first electrical insulating layer and a second opening extended through the second electrical insulating layer are defined by removing selectively a first region of the first electrical insulating layer and a second region of the second electrical insulating layer.

Abstract translation: 提供一种用于制造集成电路器件的方法，制造半导体器件的方法以及由此制造的半导体器件，以在接触孔的内部稳定地形成接触插塞，所述接触孔形成在硅化物层的上表面上，或在 硅化物层 第一，第二和第三晶体管形成在半导体衬底（100）上。 第一和第二晶体管被具有高内应力特性的第一电绝缘层覆盖，以对第一晶体管的沟道区施加拉应力或压应力。 第二和第三晶体管被具有高内应力特性的第二电绝缘层覆盖，以向第三晶体管的沟道区施加拉应力或压应力。 第一开口由第二电绝缘层限定，通过选择性地移除第二电绝缘层的第一区域，以在第二晶体管的栅极电极侧延伸。 通过第一电绝缘层延伸的第一开口和延伸穿过第二电绝缘层的第二开口通过选择性地移除第一电绝缘层的第一区域和第二电绝缘层的第二区域来限定。