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公开(公告)号：KR1020120042054A
公开(公告)日：2012-05-03
申请号：KR1020100103532
申请日：2010-10-22
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L23/5222 , H01L27/10817 , H01L27/10852 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A capacitor and a manufacturing method thereof are provided to prevent a bottom electrode to fall down by inserting a second electric conduction pattern in the inner side of a first electric conduction pattern and multiplying contact area between the first conductive pattern and the second conductive pattern. CONSTITUTION: An inter-layer insulating film(113) covering a gate line(111) and a bit line is formed on a semiconductor substrate(100). A contact plug(115) which is electrically connected to source/drain electrode of a transistor is formed on the inter-layer insulating film. A first mold layer including a bottom insulating layer(123) is formed on the inter-layer insulating film in which the contact plug is formed. First opening parts which expose the contact plug by patterning the first mold layer is formed. A first conductive pattern(132) of a cylinder type is respectively formed on the first opening parts. A core support pattern(142) is formed within the first conductive pattern.
Abstract translation: 目的：提供电容器及其制造方法，以通过在第一导电图案的内侧插入第二导电图案并且使第一导电图案与第二导电图案之间的接触面积相乘来防止底部电极掉落 。 构成：在半导体衬底（100）上形成覆盖栅极线（111）和位线的层间绝缘膜（113）。 在层间绝缘膜上形成与晶体管的源/漏电极电连接的接触插头（115）。 在形成有接触插塞的层间绝缘膜上形成包括底部绝缘层（123）的第一模制层。 形成通过图案化第一模具层而露出接触插塞的第一开口部分。 圆筒型的第一导电图案（132）分别形成在第一开口部分上。 在第一导电图案内形成芯支撑图案（142）。
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公开(公告)号：KR1020100121258A
公开(公告)日：2010-11-17
申请号：KR1020090040326
申请日：2009-05-08
Applicant: 삼성전자주식회사
IPC: H01L21/203 , H01L21/28 , H01L21/24
CPC classification number: H01L23/53266 , C23C14/185 , C23C14/3414 , H01L21/28088 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A sputtering target and a semiconductor device fabricated using the same are provided to minimize the role of Ni atom which distributes the movement of an electron by forming the content of Ni atom of W-Ni alloy thin film from over 0.01% to blow 1%. CONSTITUTION: An insulating layer(110) is formed on a substrate(100). A barrier layer(120) is formed on the insulating layer. A seed layer(130) is formed on the barrier layer. A conductive layer(200) is formed on the seed layer. The conductive layer is laminated with the sputtering method using the sputtering target.
Abstract translation: 目的：提供溅射靶和使用其制造的半导体器件，以通过将W-Ni合金薄膜的Ni原子的含量从0.01％增加到吹塑1来最小化分布电子移动的Ni原子的作用 ％。 构成：在基板（100）上形成绝缘层（110）。 在绝缘层上形成阻挡层（120）。 种子层（130）形成在阻挡层上。 在种子层上形成导电层（200）。 使用溅射靶用溅射法层叠导电层。
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公开(公告)号：KR1020100093859A
公开(公告)日：2010-08-26
申请号：KR1020090012973
申请日：2009-02-17
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/20
CPC classification number: H01L27/10891
Abstract: PURPOSE: The manufacturing method of the semiconductor device having imbedded wiring line selectively forms the low resistance wiring material on the barrier film by using the optional deposition. The imbedded wiring line is formed within the trench. CONSTITUTION: The pad insulating film(120) and hard mask layer(140) are formed on the semiconductor substrate(110). The buffer layer(130) is formed between the pad insulating film and hard mask layer. The active area of the semiconductor substrate is etched and the trench(150) is formed. The first conductive film is formed in the side and bottom surface of the trench. The second conductive film is selectively formed in the first conductive film in order to be buried to the trench.
Abstract translation: 目的：具有嵌入布线的半导体器件的制造方法通过使用任选的沉积在阻挡膜上选择性地形成低电阻布线材料。 嵌入的布线形成在沟槽内。 构成：在半导体衬底（110）上形成衬垫绝缘膜（120）和硬掩模层（140）。 缓冲层（130）形成在焊盘绝缘膜和硬掩模层之间。 蚀刻半导体衬底的有源区，形成沟槽（150）。 第一导电膜形成在沟槽的侧表面和底表面中。 第二导电膜选择性地形成在第一导电膜中以便被埋入到沟槽中。
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公开(公告)号：KR1020090132801A
公开(公告)日：2009-12-31
申请号：KR1020080058959
申请日：2008-06-23
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/4933 , H01L21/28061 , H01L27/10873
Abstract: PURPOSE: A gate structure, a forming method thereof, and a semiconductor device including the same are provided to prevent the increase of the sheet resistance of a metal film by forming a nitrification prevention film between a metal film and a nitrification film mask. CONSTITUTION: A gate insulation film(105) is formed on a substrate(100). A polysilicon film(110) is formed on the gate insulation film. A metal film(120) is formed on the polysilicon film. The metal silicide nitrification film is formed on the metal film. The metal silicide nitrification film includes one of tungsten, tantalum, titanium, cobalt, molybdenum, hafnium, ad nickel. The thickness of the metal silicide nitrification film is 5 to 100 angstrom.
Abstract translation: 目的：提供一种栅极结构及其形成方法和包括该栅极结构的半导体器件，以通过在金属膜和硝化膜掩模之间形成防硝化膜来防止金属膜的薄层电阻增加。 构成：在基板（100）上形成栅极绝缘膜（105）。 在栅极绝缘膜上形成多晶硅膜（110）。 在多晶硅膜上形成金属膜（120）。 金属硅化物硝化膜形成在金属膜上。 金属硅化物硝化膜包括钨，钽，钛，钴，钼，铪，镍中的一种。 金属硅化物硝化膜的厚度为5〜100埃。
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公开(公告)号：KR1020080051354A
公开(公告)日：2008-06-11
申请号：KR1020060122266
申请日：2006-12-05
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/4941 , H01L21/28105
Abstract: A gate electrode for a semiconductor device and a method of fabricating a semiconductor device are provided to fabricate a semiconductor device highly doped with boron ion by preventing the reaction between the boron ion and titanium. A polysilicon layer(420a) formed on a gate dielectric of a semiconductor substrate(400) is implanted with boron ions. A first conductive layer(430a) of cobalt is formed on the polysilicon layer, and then a second conductive layer(450a) of cobalt is formed on the first conductive layer. A third conductive layer is formed on the second conductive layer, and then the third conductive layer, the second conductive layer, the first conductive layer, the polysilicon layer and the gate dielectric layer are sequentially patterned to form a gate electrode.
Abstract translation: 提供一种用于半导体器件的栅电极和制造半导体器件的方法，以通过防止硼离子和钛之间的反应来制造高掺杂硼离子的半导体器件。 在半导体衬底（400）的栅极电介质上形成的多晶硅层（420a）注入硼离子。 在多晶硅层上形成钴的第一导电层（430a），然后在第一导电层上形成钴的第二导电层（450a）。 在第二导电层上形成第三导电层，然后依次构图第三导电层，第二导电层，第一导电层，多晶硅层和栅极电介质层，形成栅电极。
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Patent Agency Ranking
公开(公告)号：KR1020080044504A
公开(公告)日：2008-05-21
申请号：KR1020060113436
申请日：2006-11-16
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76831 , H01L21/02271 , H01L21/76805 , H01L21/76843
Abstract: A semiconductor device and a method of fabricating the same are provided to prevent diffusion of fluorine to an interface of an interlayer dielectric and a semiconductor substrate by forming a spacer on a sidewall of a recessed part, whose upper side makes a tight contact with the interlayer dielectric, thereby preventing formation of tungsten nitride on the interface. A method of fabricating a semiconductor device comprises the steps of: forming an interlayer dielectric(102) on a semiconductor substrate(100); forming a contact hole(104) that exposes a surface of the semiconductor substrate on the interlayer dielectric; forming a recessed part(104a) formed by an extension of the contact hole; and forming a spacer(106a) which exposes a bottom of the recessed part on a sidewall of the recessed part, by forming an oxide layer in the recessed part and anisotropically etching the oxide layer, wherein the contact hole and recessed part are filled with a conductive material which contains a barrier metal and tungsten on the barrier metal.
Abstract translation: 提供了一种半导体器件及其制造方法，以通过在凹部的侧壁上形成间隔物来防止氟向层间绝缘体和半导体基板的界面扩散，该凹部的上侧与中间层紧密接触 电介质，从而防止在界面上形成氮化钨。 制造半导体器件的方法包括以下步骤：在半导体衬底（100）上形成层间电介质（102）; 形成在所述层间电介质上露出所述半导体衬底的表面的接触孔（104） 形成由所述接触孔的延伸部形成的凹部（104a） 以及通过在所述凹部中形成氧化物层并且各向异性地蚀刻所述氧化物层而形成在所述凹部的侧壁上露出所述凹部的底部的间隔物（106a），所述接触孔和凹部填充有 在阻挡金属上含有阻挡金属和钨的导电材料。
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公开(公告)号：KR1020080040487A
公开(公告)日：2008-05-08
申请号：KR1020060108524
申请日：2006-11-03
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: A method for manufacturing a semiconductor device is provided to improve electrical characteristics of the semiconductor device by reducing remarkably an interlayer interface resistance. A polysilicon layer(120) including a first impurity is formed on a semiconductor substrate(100). A metal silicide layer(130) is formed on the polysilicon layer. A photoresist pattern(140) is formed on the metal silicide layer. A first impurity region and a second impurity region are defined by supplying second impurity ions onto the polysilicon layer exposed by the photoresist pattern. The photoresist pattern is removed. The metal silicide layer is composed of a tungsten silicide layer. The tungsten silicide layer is formed by using a physical vapor deposition method.
Abstract translation: 提供一种用于制造半导体器件的方法，以通过显着地降低层间界面电阻来改善半导体器件的电特性。 在半导体衬底（100）上形成包括第一杂质的多晶硅层（120）。 在多晶硅层上形成金属硅化物层（130）。 在金属硅化物层上形成光致抗蚀剂图案（140）。 通过将第二杂质离子提供到由光致抗蚀剂图案暴露的多晶硅层上来限定第一杂质区和第二杂质区。 去除光致抗蚀剂图案。 金属硅化物层由硅化钨层构成。 通过使用物理气相沉积法形成硅化钨层。
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公开(公告)号：KR100824406B1
公开(公告)日：2008-04-22
申请号：KR1020060107339
申请日：2006-11-01
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568 , H01L29/66825 , H01L29/66833
Abstract: A method for manufacturing a semiconductor device is provided to cure damage of a gate pattern due to an etch process and to prevent oxidation of a metal nitride layer and a tungsten electrode. A gate pattern(G) including a tunneling insulating layer(110), a metal nitride layer(140), and a metal layer(160) is formed on a semiconductor substrate(100). A selective re-oxidation process for the gate pattern is performed under gas atmosphere including hydrogen, oxygen, and nitrogen. The gate pattern includes a charge storage layer(120) and a blocking insulating layer(130) between the tunnel insulating layer and the metal nitride layer. The charge storage layer includes a silicon nitride layer. The blocking insulating layer includes an aluminum oxide layer. The metal nitride layer includes TaN or TiN.
Abstract translation: 提供一种用于制造半导体器件的方法，用于固化由蚀刻工艺引起的栅极图案的损坏并防止金属氮化物层和钨电极的氧化。 在半导体衬底（100）上形成包括隧道绝缘层（110），金属氮化物层（140）和金属层（160）的栅极图案（G）。 在包括氢，氧和氮的气体气氛下进行栅极图案的选择性再氧化工艺。 栅极图案包括在隧道绝缘层和金属氮化物层之间的电荷存储层（120）和阻挡绝缘层（130）。 电荷存储层包括氮化硅层。 阻挡绝缘层包括氧化铝层。 金属氮化物层包括TaN或TiN。
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公开(公告)号：KR1020080019982A
公开(公告)日：2008-03-05
申请号：KR1020060082611
申请日：2006-08-30
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/66825 , H01L21/28273 , H01L29/42324
Abstract: A method for manufacturing a semiconductor device is provided to prevent abnormal expansion between lateral surfaces of a tungsten silicide gate of a gate electrode by performing a re-oxidation process of the gate electrode. A gate electrode is formed on a semiconductor wafer(100). A plasma forming process is performed to form plasma including activation ions to cure damage of a sidewall of the semiconductor wafer and the gate electrode. An orientation is applied to the activation ions in a practically perpendicular direction to a surface of the semiconductor wafer. An oxide layer(130) is formed on a surface of the semiconductor wafer and a surface of the gate electrode by performing a re-oxidation process using the activation ions having the orientation.
Abstract translation: 提供一种制造半导体器件的方法，以通过执行栅电极的再氧化处理来防止栅电极的硅化钨栅极的侧表面之间的异常膨胀。 在半导体晶片（100）上形成栅电极。 执行等离子体形成处理以形成包括活化离子的等离子体，以固化半导体晶片和栅电极的侧壁的损坏。 在与半导体晶片的表面实际垂直的方向上对激活离子施加取向。 通过使用具有取向的活化离子进行再氧化处理，在半导体晶片的表面和栅电极的表面上形成氧化物层（130）。
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公开(公告)号：KR1020070050254A
公开(公告)日：2007-05-15
申请号：KR1020050107619
申请日：2005-11-10
Applicant: 삼성전자주식회사
CPC classification number: B01J19/129 , B01J2219/0894 , H01L21/28185
Abstract: 반도체 소자 제조 공정 중 발생된 수소 가스를 보다 효과적으로 제거할 수 있는 반도체 소자 제조 방법이 제공된다. 반도체 소자 제조 방법은 기판이 언로딩되고 수소 가스가 잔류하는 챔버 내부로 산소 가스 또는 오존 가스를 주입하고, 챔버 내에 플라즈마를 발생시켜 잔류하는 수소 가스를 OH 라디칼 형태로 제거하는 것을 포함한다.
수소 가스, OH 라디칼, 플라즈마Abstract translation: 提供了一种能够更有效地去除在半导体器件制造过程中产生的氢气的半导体器件制造方法。 一种制造半导体器件的方法包括：衬底到卸载和引入氢气和氧气或臭氧气体的进入残留在腔室中，并除去在OH基的形式产生在腔室中的等离子体的剩余氢气。
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