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公开(公告)号：KR1020140083528A
公开(公告)日：2014-07-04
申请号：KR1020120153405
申请日：2012-12-26
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L21/28282 , H01L21/76224 , H01L21/823487 , H01L29/7926
Abstract: Suggested is a semiconductor device which includes a substrate, multiple insulating layers and word line electrodes which are alternately stacked on the substrate, a channel structure which vertically penetrates the insulating layers and the word line electrodes and touches the substrate, and a cutting structure which vertically and partly cuts the upper parts of the word line electrodes and the upper part of the insulating layers. The cutting structure includes a cutting trench which vertically and partly cuts the upper part of the world line electrodes and the insulating layers, a cutting protection pattern which is conformal on both sidewalls of the cutting trench, and a cutting trap pattern which is conformal on the cutting protection pattern.
Abstract translation: 提出了一种半导体器件，其包括基板，交替堆叠在基板上的多个绝缘层和字线电极，垂直地穿透绝缘层和字线电极并接触基板的沟道结构，以及垂直 并且部分地切割字线电极的上部和绝缘层的上部。 切割结构包括切割沟槽，垂直和部分切割世界线电极和绝缘层的上部，切割保护图案在切割沟槽的两个侧壁上共形，切割陷阱图案保形在 切割保护模式。
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公开(公告)号：KR1020080051635A
公开(公告)日：2008-06-11
申请号：KR1020060123107
申请日：2006-12-06
Applicant: 삼성전자주식회사
IPC: G02F1/1345
CPC classification number: G02F1/13452 , G02F1/13306 , G02F1/136286 , G09G3/3611 , H05K2201/05
Abstract: A driving chip package and a liquid crystal display including the same are provided to reduce the size of a data driving chip package and a printed circuit board so as to decrease a manufacturing cost. A driving chip package(100) includes a base film(110), an inner lead, an outer lead, a wiring pattern(120), and at least one of signal transmitting wiring(130). The base film is made of insulation material and has a thickness ranging from 20mum to 100mum. The inner lead is formed on the base film. A driving chip is placed in the inner lead. The outer lead is formed on one side of the base film and contact to the outside. The wiring pattern is formed on the base film and connects between the inner lead and the outer lead. The wiring pattern has an input wiring and an output wiring. The signal transmitting wiring is formed on the base film and does not connect to the driving chip.
Abstract translation: 提供驱动芯片封装和包括该驱动芯片封装的液晶显示器以减小数据驱动芯片封装和印刷电路板的尺寸，以便降低制造成本。 驱动芯片封装（100）包括基膜（110），内引线，外引线，布线图案（120）和信号传输布线（130）中的至少一个。 基膜由绝缘材料制成，厚度范围从20um到100um。 内引线形成在基膜上。 驱动芯片放置在内引线上。 外引线形成在基膜的一侧并与外部接触。 布线图案形成在基膜上并连接在内引线和外引线之间。 布线图案具有输入布线和输出布线。 信号传输布线形成在基膜上并且不连接到驱动芯片。
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公开(公告)号：KR1020080022799A
公开(公告)日：2008-03-12
申请号：KR1020060086408
申请日：2006-09-07
Applicant: 삼성전자주식회사
CPC classification number: G09G3/3696 , G01K7/22 , G09G2320/041
Abstract: A driver for a display device is provided to prevent an LCD device from being damaged by an excessive source voltage by lowering an operation voltage of the LCD device, when an operation voltage for a source driver is close to a bonding temperature. A driver for a display device includes a current source(210), a current mirror circuit(220), a thermistor(225), a reference resistor(226), and an output terminal(203). The current mirror circuit delivers the current from the current source to first and second nodes. The thermistor is connected between the first node and a ground voltage and has a resistance varied according to a peripheral temperature. The reference resistor is connected between the second node and the ground voltage and has a predetermined reference resistance. The output terminal outputs the voltage of the second node to the outside.
Abstract translation: 提供一种用于显示装置的驱动器，用于当源极驱动器的操作电压接近接合温度时，通过降低LCD器件的操作电压来防止LCD器件被过度的源极电压损坏。 用于显示装置的驱动器包括电流源（210），电流镜电路（220），热敏电阻（225），参考电阻器（226）和输出端子（203）。 电流镜电路将电流从电流源传送到第一和第二节点。 热敏电阻连接在第一节点和地电压之间，并且电阻根据外围温度而变化。 参考电阻连接在第二节点和接地电压之间，具有预定的参考电阻。 输出端子将第二节点的电压输出到外部。
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公开(公告)号：KR1020080020743A
公开(公告)日：2008-03-06
申请号：KR1020060083956
申请日：2006-09-01
Applicant: 삼성전자주식회사
CPC classification number: G09G3/3688 , G09G2300/0828 , G09G2310/0286 , G09G2310/08
Abstract: A data driver and a display device having the same are provided to prevent an erroneous operation of the display device due to a small timing margin by generating an updating control signal by synchronizing with a second data clock signal. A shift register(210) shifts a horizontal start signal by synchronizing with a data clock signal from an external controller to generate a sampling signal. A first latch latches and outputs a load signal by synchronizing the data clock signal. A second latch latches and outputs an output signal from the first latch by synchronizing with the data clock signal. A logic operation unit combines the outputs from the first and second latches to output an updating control signal. A data latch unit(240) latches the data signal in response to a sampling signal and outputs and updates the latched data signal in response to the updating control signal. A DAC(Digital to Analog Converter)(250) converts the data signal from the data latch unit to an analog signal and outputs the analog signal.
Abstract translation: 提供数据驱动器及其显示装置，以通过与第二数据时钟信号同步产生更新控制信号来防止由于较小的定时裕度导致的显示装置的错误操作。 移位寄存器（210）通过与来自外部控制器的数据时钟信号同步来移动水平起始信号，以产生采样信号。 第一个锁存器通过同步数据时钟信号锁存和输出一个负载信号。 第二锁存器通过与数据时钟信号同步来锁存和输出来自第一锁存器的输出信号。 逻辑运算单元组合来自第一和第二锁存器的输出以输出更新控制信号。 数据锁存单元（240）响应于采样信号锁存数据信号，并根据更新控制信号输出并更新锁存的数据信号。 DAC（数模转换器）（250）将来自数据锁存单元的数据信号转换为模拟信号并输出模拟信号。
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Patent Agency Ranking
公开(公告)号：KR1020080017988A
公开(公告)日：2008-02-27
申请号：KR1020060079958
申请日：2006-08-23
Applicant: 삼성전자주식회사
CPC classification number: G09G3/3648
Abstract: An LCD(Liquid Crystal Display) device and an LCD driver are provided to adjust an output delay time of a data voltage by adjusting a charge sharing time by using an output delay time regulator. An LCD driver includes a timing controller(600) and an output delay time regulator(520). The timing controller generates a data load signal which is used to apply data voltages to respective data lines of an LCD panel. The delay time regulator outputs the data voltage in response to the data load signal. A charge sharing time is defined as a duration, when the data load signal is activated. An output delay time is defined as an interval from an activation timing of the data load signal to a timing, when the data voltage reaches a predetermined output voltage level. The output delay time regulator adjusts the charge sharing time to match the output delay time with a target output delay time.
Abstract translation: 提供LCD（液晶显示器）装置和LCD驱动器，通过使用输出延迟时间调节器调节电荷共享时间来调节数据电压的输出延迟时间。 LCD驱动器包括定时控制器（600）和输出延迟时间调节器（520）。 定时控制器产生用于将数据电压施加到LCD面板的相应数据线的数据负载信号。 延迟时间调节器响应于数据负载信号输出数据电压。 当数据负载信号被激活时，电荷共享时间被定义为持续时间。 当数据电压达到预定的输出电压电平时，输出延迟时间被定义为从数据加载信号的激活定时到定时的间隔。 输出延迟时间调节器调整电荷共享时间，以将输出延迟时间与目标输出延迟时间相匹配。
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公开(公告)号：KR1020070000612A
公开(公告)日：2007-01-03
申请号：KR1020050056098
申请日：2005-06-28
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: G03F7/70716 , G03F1/64 , G03F7/7085
Abstract: A semiconductor substrate exposing apparatus is provided to perform easily stably an exposure process regardless of the size of a guide frame by using a reticle stage capable of being shrunk or expanded corresponding to the guide frame. A semiconductor substrate exposing apparatus includes a light source unit(110), a reticle stage and a substrate stage. The reticle stage(140) is arranged on a first light progressing path. The reticle stage is capable of being shrunk or expanded according to the size of a pellicle, wherein the pellicle is attached to a reticle. The reticle stage is used for supporting the reticle. The substrate stage(170) is used for supporting a semiconductor substrate, so that the substrate is arranged on a second light progressing path.
Abstract translation: 提供一种半导体衬底曝光装置，通过使用能够相应于引导框架收缩或扩大的标线片台，而与导向框架的尺寸无关地轻松稳定地执行曝光处理。 半导体衬底曝光装置包括光源单元（110），标线片台和衬底台。 标线台（140）布置在第一光进行路径上。 标线片台能够根据防护薄膜的尺寸收缩或膨胀，其中防护薄膜组件附着在掩模版上。 标线台用于支撑掩模版。 基板台（170）用于支撑半导体基板，使得基板布置在第二光进行路径上。
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公开(公告)号：KR1020040107806A
公开(公告)日：2004-12-23
申请号：KR1020030038410
申请日：2003-06-13
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: PURPOSE: A method of manufacturing a semiconductor device is provided to obtain a desired photoresist pattern with an excellent profile by preventing a hard mask layer and the photoresist pattern from reacting on each other using a reaction barrier. CONSTITUTION: An insulating layer(115) is formed on a semiconductor substrate(110) with a transistor structure. A conductive layer(120) and a hard mask layer(125) are sequentially formed thereon. A reaction barrier(130) is formed on the hard mask layer. A photoresist pattern(140) is then formed on the reaction barrier. A hard mask is formed by etching selectively the reaction barrier and the hard mask layer using the photoresist pattern as an etching mask.
Abstract translation: 目的：提供一种制造半导体器件的方法，通过防止硬掩模层和光致抗蚀剂图案使用反应屏障彼此反应来获得具有优异外形的期望的光致抗蚀剂图案。 构成：在具有晶体管结构的半导体衬底（110）上形成绝缘层（115）。 在其上依次形成导电层（120）和硬掩模层（125）。 反应势垒（130）形成在硬掩模层上。 然后在反应屏障上形成光致抗蚀剂图案（140）。 通过使用光致抗蚀剂图案作为蚀刻掩模选择性地蚀刻反应势垒和硬掩模层来形成硬掩模。
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公开(公告)号：KR100393228B1
公开(公告)日：2003-07-31
申请号：KR1020010045223
申请日：2001-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11536 , H01L27/11543
Abstract: A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating layer pattern such that the conductive layer and the oxidation-blocking layer conform to the stepped pattern. A photoresist layer is formed on the oxidation-blocking layer such that the photoresist layer has an upper surface situated above the oxidation-blocking layer. A portion of the photoresist layer is dissolved, without having photo-exposed the photoresist layer, by soaking the photoresist layer in developing solution. This soaking alone, or supplemented with an etch back process, is carried out until the upper surface of the photoresist layer is situated below the upper surface of the oxidation-blocking layer on the stepped pattern. The resulting photoresist pattern exposes that part of the oxidation-blocking layer on the stepped pattern. A blocking layer pattern exposing the conductive layer is formed on the stepped pattern by removing the exposed part of the oxidation-blocking layer. The photoresist pattern is then removed. A hard mask defining a control gate is formed by oxidizing the surface of the conductive layer exposed by the blocking layer pattern. The blocking layer pattern is then removed. A control gate is formed by etching the conductive layer using the hard mask as an etch mask. The hard mask is then removed whereupon a stacked gate structure is formed.
Abstract translation: 制造闪存器件的方法使用自对准非曝光图案形成工艺。 导电层和氧化阻挡层形成在包括浮置栅极图案和栅极间绝缘层图案的阶梯图案上，使得导电层和氧化阻挡层符合阶梯图案。 在氧化阻挡层上形成光致抗蚀剂层，使得光致抗蚀剂层具有位于氧化阻挡层上方的上表面。 通过将光致抗蚀剂层浸泡在显影液中，使一部分光致抗蚀剂层溶解，而不曝光光致抗蚀剂层。 这种单独浸泡或补充回蚀刻工艺一直进行到光致抗蚀剂层的上表面位于台阶图案上的氧化阻挡层的上表面下方。 得到的光致抗蚀剂图案暴露了台阶图案上的氧化阻挡层的那部分。 通过去除氧化阻挡层的暴露部分，在台阶图案上形成暴露导电层的阻挡层图案。 然后去除光致抗蚀剂图案。 通过氧化由阻挡层图案暴露的导电层的表面来形成限定控制栅极的硬掩模。 然后去除阻挡层图案。 通过使用硬掩模作为蚀刻掩模来蚀刻导电层来形成控制栅极。 然后去除硬掩模，随后形成堆叠的栅极结构。
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公开(公告)号：KR1019990038210A
公开(公告)日：1999-06-05
申请号：KR1019970057862
申请日：1997-11-04
Applicant: 삼성전자주식회사
Inventor： 이재한
IPC: B41J2/235
Abstract: 본 발명은 잉크젯 프린터 헤드의 히터의 동작를 제어하는 히터제어장치에 관한 것으로, 본 발명의 히터제어장치(10)는 히터가열신호(NF)를 수신하여 히터가열신호가 비활성화되면 비활성화되고 히터가열신호(NF)가 활성화되면 활성화될때 부터 제1시간(t1) 경과후 활성화되는 제1예비가열신호(QA)를 출력하는 제1예비가열부(1), 히터가열신호(NF) 및 제1예비가열신호(QA)를 수신하여 히터가열신호(NF)가 비활성화되면 비활성화되고 히터가열신호(NF)가 활성화되고 제1예비가열신호(QA)가 활성화될때 부터 제2시간(t2) 경과후 활성화되는 제2예비가열신호(QB)를 출력하는 제2예비가열부(3) 및 히터가열신호(NF), 반전된 제1예비가열신호(QAB) 및 제2예비가열신호(QB)를 수신하여 히터가열신호(NF)가 비활성화되면 비활성화되고 히터가열신호(NF)가 활성화될때 반전된 제1� �비가열신호(QAB)나 제2예비가열신호(QB)가 활성화되면 활성화된 히터제어신호(PNF)를 출력하여 히터를 제어하는 히터제어신호 발생부(5)로 구성된다.
예비가열시간과 가열시간을 갖는 히터가열신호에 의하여 예비가열시간동안 히터를 가열시키고 가열시간동안 잉크의 분사가 이루어지므로써 인쇄품질을 향상시킬 수 있다.
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