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公开(公告)号：KR1020120061094A
公开(公告)日：2012-06-13
申请号：KR1020100103212
申请日：2010-10-22
Applicant: 삼성전자주식회사
Abstract: PURPOSE: An analog to digital converter and an image sensor including the same are provided to improve a working speed without the additional consumption of power or a circuit size by arranging a modulation unit including a plurality of modulators. CONSTITUTION: An analog to digital converter(1000) includes a modulation unit(1100) and a digital signal generation unit(1200). The modulation unit is arranged in one or more column lines from a plurality of column lines. The plurality of column lines respectively provides analog input signals. The modulation unit calculates the analog input signal provided from corresponding column lines. The modulation unit generates a digital bit stream signal corresponding to a part of digital signal bits in each stage. The digital signal generation unit generates a digital signal corresponding to the analog input signal by counting digital bit stream signals.
Abstract translation: 目的：提供模数转换器和包括该模数转换器的图像传感器，以通过布置包括多个调制器的调制单元来提高工作速度，而不需要额外的功率消耗或电路尺寸。 构成：模数转换器（1000）包括调制单元（1100）和数字信号生成单元（1200）。 调制单元从多条列线排列成一列或多列。 多个列线分别提供模拟输入信号。 调制单元计算从相应列线提供的模拟输入信号。 调制单元在每一级产生对应于一部分数字信号位的数字比特流信号。 数字信号生成单元通过对数字比特流信号进行计数来生成与模拟输入信号对应的数字信号。
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公开(公告)号：KR101106641B1
公开(公告)日：2012-01-18
申请号：KR1020050073467
申请日：2005-08-10
Applicant: 삼성전자주식회사
Abstract: 본 발명은 네비게이션 태스크와, 공통버퍼와, GUI 태스크사이의 상호작용을 통하여 MP3, JPEG, DivX 등 거의 모든 컨텐츠에 대하여 하나의 화면에 해당 컨텐츠의 데이터 파일 정보 및 헤더 데이터 정보를 함께 디스플레이함으로서 사용자가 원하는 데이터 파일 항목을 보다 쉽고 편리하게 실행하여 감상할 수 있다.
이를 위해 본 발명은 복수의 필드로 이루어진 화면을 갖는 디스플레이부와, 복수의 데이터 파일이 저장된 디스크와, 데이터 파일의 일반정보 및 상태정보를 저장하는 공통 버퍼와, 저장메시지에 따라 디스크에 저장된 데이터 파일의 일반정보 및 상태정보를 읽어 공통버퍼에 정보별로 구분하여 저장시키는 네비게이션 태스크와, 사용자의 명령에 따라 네비게이션 태스크에 해당 데이터 파일에 대한 저장메시지를 전송하고, 네비게이션 태스크에 의해 공통 버퍼에 저장된 정보를 읽어 디스플레이부의 각 필드별로 디스플레이시키는 GUI 태스크를 포함한다.-
公开(公告)号：KR1020110099563A
公开(公告)日：2011-09-08
申请号：KR1020100018657
申请日：2010-03-02
Applicant: 삼성전자주식회사
CPC classification number: G11C16/04
Abstract: 본 발명에 따른 상태 기반 불휘발성 메모리 장치의 에러 정정 방법은, 부호어(Codeword)를 선택된 메모리 셀들에 할당하되, 상기 부호어 중 제 1 비트 그룹을 제 1 메모리 셀에, 상기 부호어 중 제 2 비트 그룹을 제 2 메모리 셀에 할당하는 단계, 그리고 상기 부호어를 상기 선택된 메모리 셀들에 프로그램하는 단계를 포함하되, 상기 제 1 비트 그룹과 상기 제 2 비트 그룹은 각각 상기 부호어 상에서 연속되는 비트들이다.
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公开(公告)号：KR1020110017718A
公开(公告)日：2011-02-22
申请号：KR1020090075334
申请日：2009-08-14
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/30
Abstract: PURPOSE: A flash memory device, a program method thereof, and a read-out method thereof are provided to program at least N+1 bits in a single memory cell by sequentially executing a programming process for the upper program state and the lower program state of an N-th page. CONSTITUTION: A flash memory device comprises a control logic(160) and a bit level conversion control circuit(180). The control logic controls a program or read-out process regarding the first or N bit of data in response to a program command or read-out command. When the program or read-out process regarding the first or N bit of the data is completed, the bit level conversion control circuit executes a program or read-out process for an N+1 bit of the data in response to a control signal.
Abstract translation: 目的：提供一种闪速存储器件，其编程方法及其读出方法，用于通过依次执行用于上位程序状态和较低程序状态的编程处理来对单个存储器单元中的至少N + 1位进行编程 的第N页。 构成：闪速存储器件包括控制逻辑（160）和位电平转换控制电路（180）。 响应于程序命令或读出命令，控制逻辑控制关于第一或N位数据的程序或读出处理。 当关于数据的第一或N位的程序或读出处理完成时，位电平转换控制电路响应于控制信号执行数据的N + 1位的程序或读出处理。
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公开(公告)号：KR1020110017613A
公开(公告)日：2011-02-22
申请号：KR1020090075165
申请日：2009-08-14
Applicant: 삼성전자주식회사
CPC classification number: G06F11/10
Abstract: PURPOSE: A sequence replacement method and a device thereof are provided to improve the reliability of a memory device by replacing a specific sequence which is not required with a different sequence. CONSTITUTION: A sequence replacing unit(160) comprises a storage part and a sequence substitution circuit. The storage part stores an m number of sequences which are predefined. The sequence substitution circuit receives a first sequence outputted from a host. When the first sequence is the same as one among the m number of sequences, the sequence substitution circuit outputs a substitution sequence to a memory device instead of the first sequence. The substitution sequence includes pattern bits which represent the pattern of the first sequence and location bits which represent the start location of the first sequence.
Abstract translation: 目的：提供序列替换方法及其装置，通过用不同序列替换不需要的特定序列来提高存储器件的可靠性。 构成：序列替换单元（160）包括存储部分和序列替换电路。 存储部存储预定义的m个序列。 序列替换电路接收从主机输出的第一序列。 当第一序列与m个序列中的序列相同时，序列替换电路将取代序列输出到存储器件而不是第一序列。 替换序列包括表示第一序列的模式的图形比特和表示第一序列的开始位置的位置比特。
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Patent Agency Ranking
公开(公告)号：KR1020100127398A
公开(公告)日：2010-12-06
申请号：KR1020090045827
申请日：2009-05-26
Applicant: 삼성전자주식회사
CPC classification number: G11C29/82
Abstract: PURPOSE: A memory system and a bad block management method thereof are provided to improve the efficiency of a memory block. CONSTITUTION: A first step is processed to determine that a memory block satisfies a bad block condition(S110). When the memory block satisfies the bad block condition, a subsequent treatment operates in the memory block(S120). The memory block is allocated to the bad block(S130). When the bad block satisfies a bad block release condition, the bad block is released. The subsequent treatment programs a cell in the erase state into a program state cell or stores the timing to assign the memory block as the bad block.
Abstract translation: 目的：提供存储器系统及其坏块管理方法以提高存储器块的效率。 构成：处理第一步以确定存储块满足坏块条件（S110）。 当存储块满足坏块条件时，随后的处理在存储块中进行操作（S120）。 存储块被分配给坏块（S130）。 当坏块满足坏块释放条件时，坏块被释放。 随后的处理将处于擦除状态的单元编程到编程状态单元中，或存储将该存储块分配为坏块的定时。
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97.发明公开
公开(公告)号：KR1020100052159A
公开(公告)日：2010-05-19
申请号：KR1020080111056
申请日：2008-11-10
Applicant: 삼성전자주식회사
CPC classification number: G11C16/26 , G11C11/5642 , G11C29/00 , G11C2211/5634 , G11C7/1051 , G11C16/30 , G11C16/3418
Abstract: PURPOSE: A nonvolatile semiconductor memory device, a memory card thereof, a memory system thereof, and a read voltage estimation method thereof are provided to prevent data error due to the change of read voltage by estimating optimum read voltage through comparing data information during a program process and a read process. CONSTITUTION: A memory cell array(110) comprises a plurality of memory cells. A read voltage estimating unit(20) compares data information during a program process and a read process. The read voltage estimating unit estimates optimum read voltage by changing the read voltage based on the comparison result. A read voltage generating unit(10) generates a corresponding read voltage in response to a control signal of the read voltage estimating unit. A reference data storage unit stores the reference data drawn from program data.
Abstract translation: 目的：提供一种非易失性半导体存储器件，其存储卡，其存储器系统及其读取电压估计方法，以通过在程序期间比较数据信息来估计最佳读取电压，以防止由于读取电压的变化引起的数据错误 过程和阅读过程。 构成：存储单元阵列（110）包括多个存储单元。 读取电压估计单元（20）在程序处理和读取处理期间比较数据信息。 读取电压估计单元通过基于比较结果改变读取电压来估计最佳读取电压。 读取电压产生单元（10）响应于读取电压估计单元的控制信号产生相应的读取电压。 参考数据存储单元存储从程序数据中提取的参考数据。
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公开(公告)号：KR1020100006712A
公开(公告)日：2010-01-21
申请号：KR1020080067030
申请日：2008-07-10
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/24 , G11C2013/0073 , G11C2013/009 , G11C2013/0092
Abstract: PURPOSE: A memory device and a method for programming memory data are provided to reduce a stabilization time of a threshold voltage and improve distribution of the threshold voltage of memory cells by controlling the intervals and the sizes of a plurality of pulses applied to a plurality of memory cells. CONSTITUTION: A memory cell array(310) includes a plurality of memory cells. A programming unit(320) repetitively applies plus pulses and minus pulses to a plurality of memory cells. A controller controls the interval between the plus pulses and the minus pulses and the size of the pulses.
Abstract translation: 目的：提供存储器件和用于编程存储器数据的方法，以通过控制施加到多个存储器数据的多个脉冲的间隔和尺寸来减小阈值电压的稳定时间并改善存储器单元的阈值电压分布 记忆细胞 构成：存储单元阵列（310）包括多个存储单元。 编程单元（320）对多个存储单元重复地加上加脉冲和负脉冲。 控制器控制正脉冲与负脉冲之间的间隔以及脉冲的大小。
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公开(公告)号：KR1020090097673A
公开(公告)日：2009-09-16
申请号：KR1020080022963
申请日：2008-03-12
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1008 , G11C16/26
Abstract: An apparatus for detecting memory data based on a soft decision value are provided to minimize an error of data stored in a memory cell by allotting a soft decision value according to error information. In an apparatus for detecting memory data based on a soft decision value, a reference voltage determination unit(110) determines a soft decision value based on channel information of a memory cell. A voltage comparative part(120) determines a period which includes a threshold voltage by comparing the threshold voltage of the memory cell with a plurality of soft-decision reference voltages. A data detection part detects data stored in memory cell by a period where a threshold voltage is included. A pilot data storage module(140) stores pilot data of the small bit pattern in the memory cell. The data detection part detects the pilot data stored in the memory cell. A channel information estimating unit(150) estimates the channel information of the memory cell based on detected data.
Abstract translation: 提供一种用于基于软判决值检测存储器数据的装置，以通过根据错误信息分配软判定值来最小化存储在存储单元中的数据的错误。 在基于软判决值检测存储器数据的装置中，参考电压确定单元（110）基于存储器单元的信道信息来确定软判决值。 电压比较部件（120）通过将存储器单元的阈值电压与多个软判决参考电压进行比较来确定包括阈值电压的周期。 数据检测部分将存储在存储单元中的数据检测到包含阈值电压的周期。 导频数据存储模块（140）将小位模式的导频数据存储在存储单元中。 数据检测部分检测存储在存储单元中的导频数据。 信道信息估计单元（150）基于检测到的数据来估计存储单元的信道信息。
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公开(公告)号：KR1020090090063A
公开(公告)日：2009-08-25
申请号：KR1020080015310
申请日：2008-02-20
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1072 , H03M13/09 , H03M13/15 , H03M13/1515 , H03M13/152
Abstract: A memory device and a memory reading method thereof are provided to improve the performance of an error correction by performing the ECC(Error Correction Code) decoding of the data read from the multi bit cells. A memory device(100) includes a multi bit cell array(110), an error detector(120), and a data estimator(130). The error detector reads a first data page from a memory page(111) inside the multi bit cell array. The error detector performs ECC decoding of the first data page and detects the error bit of the first data page. The estimator identifies the multi bit cell with an error bit. The estimator estimates the data of the second data page stored in the identified multi bit cell.
Abstract translation: 提供了一种存储器件及其存储器读取方法，以通过执行从多位单元读取的数据的ECC（纠错码）解码来改善纠错的性能。 存储器件（100）包括多位单元阵列（110），误差检测器（120）和数据估计器（130）。 误差检测器从多位单元阵列内部的存储器页（111）读取第一数据页。 误差检测器执行第一数据页的ECC解码并检测第一数据页的错误位。 估计器使用错误位来识别多位单元。 估计器估计存储在所识别的多位单元中的第二数据页的数据。
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