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公开(公告)号：KR1019960013942B1
公开(公告)日：1996-10-10
申请号：KR1019930012202
申请日：1993-06-30
IPC: H01L29/73
Abstract: forming a trench for isolation after forming a n+ silicone layer(1) and a n- silicone layer(2) on a P type silicone wafer and a first nitrided film; forming a local insulating film(3) by thermal oxidizing an inactive region locally except an active region(4a) and a collector junction region(4b); forming a n+ layer(4) by ion-implantation into the collector junction region(4b); defining an emitter region by etching after forming a base thin film(5) and a silicide thin film(6) for a base electrode and depositing a first, a second insulating film(7,8); forming a first side wall insulating film(9); removing the second insulating film(8), the first side wall insulating film(9) and the remained base thin film(5); forming a second side wall insulating film(11) by anisotropic dry-etching after forming a fourth insulatin film; forming an emitter polysilicone layer(12a) and a collector polysilicone layer(12b) by etching a polysilicone layer(12) selectively, and depositing a fifth insulating film(13).
Abstract translation: 在P型硅晶片和第一氮化膜上形成n +硅氧烷层（1）和n-硅氧烷层（2）之后，形成用于隔离的沟槽; 通过将有源区（4a）和集电极结区（4b）以外的非活性区域热氧化来形成局部绝缘膜（3）; 通过离子注入形成n +层（4）到集电极结区（4b）中; 在形成用于基底电极的基底薄膜（5）和硅化物薄膜（6）之后通过蚀刻限定发射极区域并沉积第一绝缘膜（7,8）; 形成第一侧壁绝缘膜（9）; 去除第二绝缘膜（8），第一侧壁绝缘膜（9）和残留的基底薄膜（5）; 在形成第四绝缘膜之后通过各向异性干蚀刻形成第二侧壁绝缘膜（11）; 通过选择性地蚀刻聚硅氧烷层（12）形成发射极多硅层（12a）和集电极多硅层（12b），并沉积第五绝缘膜（13）。
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公开(公告)号：KR1019960006749B1
公开(公告)日：1996-05-23
申请号：KR1019920024461
申请日：1992-12-16
IPC: H01L29/73
Abstract: forming an burying layer (1) by injecting impurities on p-type silicone substrate and then forming a first insulating film (2) and a first polycrystalline silicone film sequentially; forming a first side film (7) by coating the insulators(4),(5),(6) sequentially and etching the above four insulators (4),(5),(6) and the above first polycrystalline silicone film (3) sequentially and then etching after coating an insulating film; forming a first oxide film (9) by thermal oxidation of upper surface of a collector layer (8) after etching the above first side film (7) and growing the collector layer; forming a second oxide film (11) by thermal oxidation of the polycrystalline silicon film (1) after etching the above first side film (7) and forming the polycrystalline silicone layer (10); growing a p+SiGe base layer (13) selectively by removing the above second oxide film (11) and the above fourth insulating film (7); and forming a second side film (14) in the side of upper surface of the above base layer (13) after removing the above third insulating film (5) with selective etching process; defining an emitter (15) with masking and etching process after making polycrystalline silicone in upper part of the second side film (14) and the above base layer (9).
Abstract translation: 通过在p型硅树脂衬底上注入杂质形成掩埋层（1），然后依次形成第一绝缘膜（2）和第一多晶硅膜; 通过依次涂覆绝缘体（4），（5），（6）并蚀刻上述四个绝缘体（4），（5），（6）和上述第一多晶硅膜（3），形成第一侧膜 ），然后在涂覆绝缘膜之后进行蚀刻; 在蚀刻上述第一侧膜（7）之后，通过集电体层（8）的上表面的热氧化形成第一氧化膜（9）并使集电体层生长; 在蚀刻上述第一侧膜（7）并形成多晶硅层（10）之后，通过多晶硅膜（1）的热氧化形成第二氧化膜（11）。 通过去除上述第二氧化膜（11）和上述第四绝缘膜（7）选择性地生长p + SiGe基层（13）。 以及在通过选择性蚀刻工艺除去上述第三绝缘膜（5）之后，在所述基底层（13）的上表面侧形成第二侧膜（14） 在第二侧膜（14）和上述基底层（9）的上部制造多晶硅以后，限定具有掩模和蚀刻工艺的发射体（15）。
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公开(公告)号：KR1019960000529B1
公开(公告)日：1996-01-08
申请号：KR1019920025011
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: H01J1/16
Abstract: forming an oxide film having a predetermined pattern on a semiconductor substrate; forming an electron emission controlling electrode of the predetermined shaped structure by etching the exposed part of the semiconductor substrate at a predetermined depth; forming an insulating film which is not thicker than the height of the controlling electrode on the top of the semiconductor and the wall of the controlling electrode; forming the conducting layer by eliminating the conducting layer which is formed on the surface of the side wall of the controlling electrode in the middle of the top of controlling electrode and the insulating film; forming a side wall conducting layer which is electrically connected with the conducting layer on the wall of the controlling electrode where the conducting layer is not formed; forming making the side wall conducting layer and the controlling electrode face each other by etching the top surface of the insulating film.
Abstract translation: 在半导体衬底上形成具有预定图案的氧化膜; 通过以预定深度蚀刻半导体衬底的暴露部分，形成预定成形结构的电子发射控制电极; 形成绝缘膜，其不比半导体顶部的控制电极的高度和控制电极的壁厚; 通过消除在控制电极的顶部的中间的控制电极的侧壁的表面上形成的导电层和绝缘膜来形成导电层; 形成与导电层未形成的控制电极的壁上的导电层电连接的侧壁导电层; 通过蚀刻绝缘膜的顶面，形成侧壁导电层和控制电极彼此面对。
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公开(公告)号：KR1019950009638B1
公开(公告)日：1995-08-25
申请号：KR1019920026629
申请日：1992-12-30
Applicant: 한국전자통신연구원
IPC: H01L41/27
Abstract: joining a first substrate including a thermal oxide film(8) fromed on an n- silicon substrate(1) and a second sustrate including a p- epitaxy layer(7) formed on a p++ silicon substrate(10) so as to bring the thermal oxide film(8) and the epitaxy layer(7) together; joining a third substrate formed by etching the p++ silicon substrate(10) and a fourth sustrate including a piezoresistor(2) and a dielectrics separating oxide film(9) formed on a silicon substrate(1a) so as to bring the epitaxy layer(7) and the dielectrics separating oxide film(9) together; etching the silicon substrate(1a) using a first silicon film(13) as a mask; forming an electrode(4) on the piezoresistor, and forming a passivation oxide film(14) and a second silicon film(13a) on the dielectrics separating oxide film(9) in turn; forming a diaphragm pattern of the silicon films(13)(13a); and forming a thin silicon diaphragm(3) by etching the n- silicon substrate(1). The method can improve an output response chracteristic to temperature, product the homogeneous diaphragm, and control the thickness of the diaphragm.
Abstract translation: 接合包括从n型硅衬底（1）上的热氧化膜（8）的第一衬底和包括形成在p ++硅衬底（10）上的p-外延层（7）的第二衬垫，以使热 氧化膜（8）和外延层（7）; 接合通过蚀刻p ++硅衬底（10）形成的第三衬底和包括形成在硅衬底（1a）上的压电电阻（2）和电介质分离氧化膜（9）的第四衬底，以使外延层（7） ）和将氧化物膜（9）分离在一起的电介质; 使用第一硅膜（13）作为掩模蚀刻硅衬底（1a）; 在所述压电电阻器上形成电极（4），并依次在所述电介质隔离氧化膜（9）上形成钝化氧化膜（14）和第二硅膜（13a） 形成硅膜（13）（13a）的光阑图案。 以及通过蚀刻所述n型硅衬底（1）形成薄的硅膜（3）。 该方法可以提高温度特性，产生均匀膜片，控制膜片厚度的输出响应。
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Patent Agency Ranking
公开(公告)号：KR1019950021035A
公开(公告)日：1995-07-26
申请号：KR1019930028671
申请日：1993-12-20
Applicant: 한국전자통신연구원
IPC: H01L21/32
Abstract: 본 발명은 X선 마스크 제조방법에 관한 것으로서, 종래에 X선 마스크에서 흡수체가 종횡비가 커서 기계적으로 불안정하고, 흡수체 자체의 박리현상까지 발생하는 문제점을 해결하기 위하여 본 발명에서는 흡수체(204)를 투과막(202)내에 매몰시킴으로써 종횡비를 가지면서, 구조적으로 안정한 X선 마스크를 제작할 수가 있다.
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公开(公告)号：KR1019950008254B1
公开(公告)日：1995-07-26
申请号：KR1019920024459
申请日：1992-12-16
IPC: H01L29/80
Abstract: The method reduces the surface recombination of base current by forming a guiding layer of a precise thickness. The method comprises the steps of: forming an emitter mesa struture of n+-type GaAs layer on the n--type AlGaAs layer; forming a base mesa structure of p+-type GaAs layer on the n--type GaAs layer; and including an AlGaAs guiding layer (12) which is formed by the implantation of aluminum into the surface of the base mesa structure.
Abstract translation: 该方法通过形成精确厚度的引导层来减小基极电流的表面复合。 该方法包括以下步骤：在n型AlGaAs层上形成n +型GaAs层的发射极台面; 在n型GaAs层上形成p +型GaAs层的基台面结构; 并且包括通过将铝注入基底台面结构的表面而形成的AlGaAs导向层（12）。
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公开(公告)号：KR1019950020834A
公开(公告)日：1995-07-24
申请号：KR1019930029625
申请日：1993-12-24
Applicant: 한국전자통신연구원
IPC: H01H59/00
Abstract: 본 발명은 10V이하의 저전압에서 작동이 가능하고, 응답속도가 100㎲ec이하인 고속 캔티레버(Cantilever)형 정전력 구동 마이크로 릴레이 구조 및 제작방법에 관한 것으로 마이크로 머시닝 기술을 이용하여 저전압(10V이항), 고속 응답성(100㎲ec)특성을 갖도록 하기 위하여 마이크로 릴레이구조는 SiO
2 절연체상에 전극금속박막이 형성된 캔티레버(Cantilever)형태이고 10V이하의 저전압으로 구동하기 위하여 전극간 거리를 2㎛정도를 하고, 실장시 사용되는 상부 덮개판을 캔티레버(Cantilever)를 하부방향으로 변형하여 구동발생력을 극대화할 수 있도록 하여 릴레이의 접점의 저저항 유지 및 작동수평 증가를 위해서 상부 덮개판에 액체금속인 수은을 사용함을 특징으로 한다.-
公开(公告)号：KR1019950001620B1
公开(公告)日：1995-02-27
申请号：KR1019910024258
申请日：1991-12-24
IPC: H01L35/00
Abstract: The method includes the steps of growing a SixGe1-x thin film (1) on a silicon substrate (4), growing a Ge thin film (2) on the SixGe1-x thin film (1), and growing a GaAs thin film (3) on the Ge thin film (2), thereby forming the SixGe1-x and Ge thin films (1,2) between the Si substrate and the GaAs layer to reduce the lattice mismatch between Si and GaAs.
Abstract translation: 该方法包括以下步骤：在硅衬底（4）上生长SixGe1-x薄膜（1），在SixGe1-x薄膜（1）上生长Ge薄膜（2），并生长GaAs薄膜 3），从而在Si衬底和GaAs层之间形成SixGe1-x和Ge薄膜（1,2），以减少Si和GaAs之间的晶格失配。
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公开(公告)号：KR1019950004608A
公开(公告)日：1995-02-18
申请号：KR1019930014240
申请日：1993-07-26
Applicant: 한국전자통신연구원
IPC: H01L29/86
Abstract: 본 발명은 반도체장치의 기술에 관한 것으로서, 구체적으로는 전기적으로 프로그램가능한 안티-퓨즈 소자(electrically antifuse elements) 및 이를 제조하는 방법에 관한 것으로, 기능소자가 형성된 반도체기판(1)상에 층간막을 사이에 두고 이층구조의 전극을 형성하는 전기적으로 프로그램가능한 안티-퓨즈 소자에 있어서, 상기 반도체기판(1)상에 형서오딘 필드산화막(2)과, 상기 필드산화막(2)상에 소정패턴으로 형성된 제 1 전극(3)과, 상기 제 1 전극(3)의 양단의 상부를 걸치면서 상기 필드산화막(2)상에 형성된 제 1 절연막(4)과, 상기 제 1 절연막(4) 사이에서 상기 제 1 전극(3)의 노출된 표면상에 형성되어 상기 층간막으로 사용된 제 2 절연막(5)과, 상기 제 2 절연막(5)상에 제 2 전극(6)을 포함하는 것이다.
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