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99 records (took 0.027 seconds)

    93.
    发明专利
    未知

    公开(公告)号：DE10222892A1

    公开(公告)日：2003-12-11

    申请号：DE10222892

    申请日：2002-05-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： CHRISSOSTOMIDIS IOANNIS ,  GRAF VON KEYSERLINGK ALBERT ,  SCHNEIDER HELMUT

    IPC: G11C7/10 ,  G11C7/22

    Abstract: An integrated memory has a respective terminal for a clock signal and a data clock signal and also a data terminal. For a write operation, the memory accepts a write command on account of the clock signal and, in a manner time-delayed with respect thereto, a plurality of data at the data terminal on account of the data clock signal. An access controller serves for controlling an access to a memory cell array of the memory for the parallel writing of the accepted data to selected memory cells. The access to the memory cell array is triggered by the access controller by a phase-shifted clock signal before the clock signal has a next rising edge after the acceptance of the data. It is thus possible to increase the effective writing time from the application of the write command to the closing of a memory bank by a precharge command.

    96.
    发明专利
    未知

    公开(公告)号：DE10134178A1

    公开(公告)日：2003-01-30

    申请号：DE10134178

    申请日：2001-07-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT

    IPC: H01L27/105

    Abstract: The invention relates to a semiconductor memory (1) having a plurality of memory-cell arrays (2), a plurality of sense-amplifier areas (3) and a plurality of driver areas (4) on a semiconductor substrate (7) of a first conductivity type, each of the multiple sense-amplifier areas (3) and multiple driver areas (4) containing at least one first well (9) of the first conductivity type and/or at least one second well (10) of a second conductivity type, and each first well (9) of the driver areas (4) being isolated from the semiconductor substrate (7) by a buried horizontal layer (8) of the second conductivity type.In order to ensure less space is required, the semiconductor memory according to the invention exhibits the features that the buried horizontal layer (8) extends continuously beneath at least all the memory-cell arrays (2) and the multiple driver areas (4) of the semiconductor memory (1), and that a separation (6) is provided between the second well (10) and the buried horizontal layer (8) so that the second well (10) is electrically isolated from the buried horizontal layer (8). Semiconductor memory having a plurality of memory-cell arrays

    97.
    发明专利
    未知

    公开(公告)号：DE19963502A1

    公开(公告)日：2001-07-12

    申请号：DE19963502

    申请日：1999-12-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHOENIGER SABINE ,  SCHNEIDER HELMUT

    IPC: G11C11/407 ,  G11C7/06 ,  G11C7/10 ,  G11C8/18 ,  G11C11/408 ,  G11C7/00

    Abstract: An integrated-circuit circuit arrangement has storage/memory cells (MC) arranged in a storage location array and combined into addressable units with columns of bit lines (BL) and rows of word lines (WL). A decoder (10) selects a bit line (BL) which is connected to a column (bit-line) select line (11) for transmission of a column select signal (S11), and which has a connection (12) for an input signal (S12) for activating the column select signal (S11), and a connection (21) for a row (word-line) activation signal (S21) for activating a row access- signal sequence (S22,S23). The connection (12) for the decoder (10) input signal (S12) is joined to a connection (22) for at least one signal (S22) out of the row (word-line) access-signal sequence (S22,S23) which indicates with its status that the row access is concluded.

    98.
    发明专利
    未知

    公开(公告)号：DE19960247A1

    公开(公告)日：2001-06-21

    申请号：DE19960247

    申请日：1999-12-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

    IPC: G11C7/10 ,  G11C7/20 ,  G11C11/00 ,  G11C11/4091 ,  G11C11/56 ,  G11C14/00 ,  G11C11/4063 ,  G11C29/00

    Abstract: The invention relates to a data storage device, comprising a plurality of storage cells for storing data which are represented by a first physical value of the storing storage elements of the storage cells, especially their conductivity or charge, said storage elements being configured especially in the form of a storage capacitor. A detection device is provided for detecting the first physical value representing the data and a second detection device is provided for detecting a second physical value of the storage cells or constituents of the same, especially of the storage element, especially the leakage current of the storage capacitor provided for storing the data. Said second physical value represents a second detectable item of information in addition to the first physical value representing the data, independently of said first physical value . The invention also relates to a method for permanently storing information in storage cells of a data storage device for reversibly or permanently storing data.

    Semiconductor body conductor-paths wiring arrangement
    99.
    发明专利
    Semiconductor body conductor-paths wiring arrangement 未知

    公开(公告)号：DE19948570A1

    公开(公告)日：2001-04-19

    申请号：DE19948570

    申请日：1999-10-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

    IPC: G03F1/00 ,  H01L21/768 ,  H01L23/522

    Abstract: An arrangement for wiring of conductor paths (1-4) fabricated by the use of phase-masks with alternating phase on a given metallisation plane, such that a first conductor path (2) fabricated with a phase-mask of a first phase is adjacent to a second conductor path (3') fabricated with a phase-mask of a second phase, opposite to the first phase, so that a discontinuity in the wiring formed from the first and the second conductor paths (2,3'), results at the point of connection between the first (2) and the second (3') conductor paths. The connection between the first (2) and the second (3') conductor paths is achieved through a connection contact (7) located underneath or above the specified metallisation plane, the connection contact consisting specifically of doped polycrystalline silicon.

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