公开(公告)号：DE50104949D1

公开(公告)日：2005-02-03

申请号：DE50104949

申请日：2001-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRISSOSTOMIDIS IOANNIS ,  SCHAFFROTH THILO ,  FISCHER DR

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4091

Abstract: The circuit has a first current path for activation of the memory via an addressed word line, a second current path in which a read amplifier control signal is generated by a controler from a signal (RAVLD) derived from the first current path and a voltage supply device for components of the two current paths. Thick oxide transistors (T) supplied with an increased supply voltage are provided in the second path in addition to thin oxide transistors (T') supplied with a normal voltage.

公开(公告)号：DE10106486A1

公开(公告)日：2002-08-29

申请号：DE10106486

申请日：2001-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  CHRISSOSTOMIDIS IOANNIS

IPC: H03K3/011 ,  H03K3/0231 ,  H03K3/0232 ,  H03K3/57

Abstract: The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C') which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C') which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C') can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.

公开(公告)号：DE10106486C2

公开(公告)日：2003-02-27

申请号：DE10106486

申请日：2001-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  CHRISSOSTOMIDIS IOANNIS

IPC: H03K3/011 ,  H03K3/0231 ,  H03K3/0232 ,  H03K3/57

Abstract: The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C') which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C') which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C') can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.

公开(公告)号：DE10051613C2

公开(公告)日：2002-10-24

申请号：DE10051613

申请日：2000-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS ,  SCHAFFROTH THILO

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4091 ,  G11C5/14

Abstract: The circuit has a first current path for activation of the memory via an addressed word line, a second current path in which a read amplifier control signal is generated by a controler from a signal (RAVLD) derived from the first current path and a voltage supply device for components of the two current paths. Thick oxide transistors (T) supplied with an increased supply voltage are provided in the second path in addition to thin oxide transistors (T') supplied with a normal voltage.

公开(公告)号：DE10222892B4

公开(公告)日：2008-04-24

申请号：DE10222892

申请日：2002-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRISSOSTOMIDIS IOANNIS ,  GRAF VON KEYSERLINGK ALBERT ,  SCHNEIDER HELMUT

IPC: G11C7/22 ,  G11C7/10

Abstract: An integrated memory has a respective terminal for a clock signal and a data clock signal and also a data terminal. For a write operation, the memory accepts a write command on account of the clock signal and, in a manner time-delayed with respect thereto, a plurality of data at the data terminal on account of the data clock signal. An access controller serves for controlling an access to a memory cell array of the memory for the parallel writing of the accepted data to selected memory cells. The access to the memory cell array is triggered by the access controller by a phase-shifted clock signal before the clock signal has a next rising edge after the acceptance of the data. It is thus possible to increase the effective writing time from the application of the write command to the closing of a memory bank by a precharge command.

公开(公告)号：DE10120672A1

公开(公告)日：2002-11-07

申请号：DE10120672

申请日：2001-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS

IPC: G11C7/10 ,  G11C11/412

Abstract: Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which has a first voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit signal, a potential isolating transistor having a control connection at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data bit input signal as a data bit output signal having a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for storage of the data bit.

公开(公告)号：DE10222892A1

公开(公告)日：2003-12-11

申请号：DE10222892

申请日：2002-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRISSOSTOMIDIS IOANNIS ,  GRAF VON KEYSERLINGK ALBERT ,  SCHNEIDER HELMUT

IPC: G11C7/10 ,  G11C7/22

Abstract: An integrated memory has a respective terminal for a clock signal and a data clock signal and also a data terminal. For a write operation, the memory accepts a write command on account of the clock signal and, in a manner time-delayed with respect thereto, a plurality of data at the data terminal on account of the data clock signal. An access controller serves for controlling an access to a memory cell array of the memory for the parallel writing of the accepted data to selected memory cells. The access to the memory cell array is triggered by the access controller by a phase-shifted clock signal before the clock signal has a next rising edge after the acceptance of the data. It is thus possible to increase the effective writing time from the application of the write command to the closing of a memory bank by a precharge command.

公开(公告)号：DE10120672C2

公开(公告)日：2003-03-20

申请号：DE10120672

申请日：2001-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS

IPC: G11C7/10 ,  G11C11/412

Abstract: Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which has a first voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit signal, a potential isolating transistor having a control connection at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data bit input signal as a data bit output signal having a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for storage of the data bit.

公开(公告)号：DE10051613A1

公开(公告)日：2002-05-02

申请号：DE10051613

申请日：2000-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS ,  SCHAFFROTH THILO

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4091 ,  G11C5/14

Abstract: The circuit has a first current path for activation of the memory via an addressed word line, a second current path in which a read amplifier control signal is generated by a controler from a signal (RAVLD) derived from the first current path and a voltage supply device for components of the two current paths. Thick oxide transistors (T) supplied with an increased supply voltage are provided in the second path in addition to thin oxide transistors (T') supplied with a normal voltage.