公开(公告)号：JP2000340099A

公开(公告)日：2000-12-08

申请号：JP14673999

申请日：1999-05-26

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： HONDA YOSHIAKI ,  AIZAWA KOICHI ,  KOMODA TAKUYA ,  OKA NAOMASA ,  ICHIHARA TSUTOMU ,  HATAI TAKASHI ,  WATABE YOSHIFUMI ,  KONDO YUKIHIRO

IPC: H01J1/312 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

Abstract: PROBLEM TO BE SOLVED: To provide a field emission type electron source capable of emitting electrons from a desired region of a surface electrode and to provide its manufacturing method. SOLUTION: This field emission type electron source 10 is provided with: a p-type silicon substrate 1 of a conductive substrate; n-type regions 8 of diffusion layers formed in a stripe-like form on the main surface side in the p-type silicon substrate 1; electric field drift layers 6 which are formed on the n-type regions 8 with an oxidized porous polycrystalline silicon and in which electrons injected from the n-type regions 8 drift; polycrystalline silicon layers 3 formed between the electric field drift layers 6; and surface electrodes 7 which are formed in a stripe-like form in the direction intersecting with the n-type regions 8 and formed of conductive thin films formed straddling on the electric field drift layers 6 and on the polycrystalline silicon layers 3. A p++ type region 17 of a p-type region having high impurity concentration is formed nearly at the middle part between the n-type regions 8 on the main surface side in the p-type silicon substrate 1.

公开(公告)号：JP2000286264A

公开(公告)日：2000-10-13

申请号：JP8970399

申请日：1999-03-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKUTO TAKASHI ,  OKA NAOMASA ,  OGIWARA ATSUSHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming aluminum wiring whose surface conditions are satisfactory. SOLUTION: This formation method includes a process of forming an insulating layer 2 on one main surface of a semiconductor substrate 1, a process of forming aluminum wiring including silicon on the insulating layer 2 by sputtering, and a process of forming a passivation film 4 on the insulating layer 2 and an aluminum wiring 3. In this case, the surface part (surface of a pad) of the location, where the passivation him 4 is not made of the aluminum wiring 3, is removed.

公开(公告)号：JPH11312662A

公开(公告)日：1999-11-09

申请号：JP11913198

申请日：1998-04-28

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA ,  OKUTO TAKASHI

IPC: H01L21/306 ,  H01L21/304 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To provide the processing method of a semiconductor substrate, wherein the dispersion in the digging depth by etching is eliminated. SOLUTION: Between a first semiconductor layer 1 and the second semiconductor layer 3, an intermediate layer 2 which comprises the material whose etching rate is larger than that of first and second a semiconductor layers 1 and 3 with respect to first etching method, is formed, and a semiconductor substrate is formed. Of the first and second semiconductor layers 1 and 3, one semiconductor layer is partially etched, until the layer reaches the intermediate layer 2 by the second etching method. Then, etching is performed until a bottom part 5 of the intermediate layer 2 reaches the other semiconductor layer by the first etching method.

公开(公告)号：JPH11298000A

公开(公告)日：1999-10-29

申请号：JP10515298

申请日：1998-04-15

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKUTO TAKASHI ,  SUZUKI YUJI ,  OKA NAOMASA ,  OGIWARA ATSUSHI

IPC: H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power MOSFET, which has each electrode on the major front plane and has a low on-resistance, and to provide a method for manufacturing such power MOSFET. SOLUTION: On the major front plane of an (n) type silicon substrate 1, (p) type well regions 2a, 2b and 2c which are separated by trenches 9, and an (n) type drain region 4 are formed at an interval. On each of the major front planes of the (p) type well regions 2a, 2b and 2c, (n) type source regions 3a, 3b and 3c are respectively formed. A gate electrode 7 is formed on the inner circumference plane of the trench through a gate oxide film 5.

公开(公告)号：JPH1197356A

公开(公告)日：1999-04-09

申请号：JP25740297

申请日：1997-09-24

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： KAMAKURA MASAARI ,  OKA NAOMASA ,  OGIWARA ATSUSHI ,  OKUTO TAKASHI

IPC: H01L21/205

Abstract: PROBLEM TO BE SOLVED: To suppress forming of an inverted layer due to auto doping, by mounting on a susceptor a semiconductor substrate having a high-concn. second conductivity type buried victim layer, and semiconductor substrate contg. a first conductivity type impurity at a high concn. through the epitaxial growth. SOLUTION: A manufacturing method comprises steps of depositing and thermally diffusing a p-type impurity, using a field oxide film having openings as a mask to form a p-through buried victim layer, etching to perfectly remove the field oxide film, and forming an epitaxial layer on the p-through buried victim layer of an Si substrate 1, wherein this substrate 1 having the victim layer and another Si substrate 2 contg. P or other n-type impurity at a high concn. are mounted on a susceptor S of an induction heating epitaxial growth apparatus, and the susceptor S is rotated with center at a rotary shaft 3 during forming of the epitaxial on the substrate 1.

公开(公告)号：JPH10335466A

公开(公告)日：1998-12-18

申请号：JP13691897

申请日：1997-05-27

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA ,  KAMAKURA MASATOMO ,  OGIWARA ATSUSHI ,  OKUTO TAKASHI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabrication method which can adjust the resistance value with high precision. SOLUTION: An n+type impurity region 2 is formed in a single-crystal silicon substrate 1 such that the region 2 encloses a V-shaped trench portion 1a formed on one main surface of the single-crystal silicon substrate 1. A phosphorus (P) rich polycrystal silicon layer 4 is formed at the surface side on which the trench portion 1a of the polycrystal substrate 1 is formed by way of a silicon oxide film 3 having a thin film thickness. The silicon oxide film 3 is formed in such a manner that the film thickness becomes thinnest at the bottom portion of the trench portion 1a and the polycrystal silicon layer 4 is disposed at the portion where the trench portion 1a is formed. An interlayer insulation film 5 is formed on the silicon oxide film 3 and the polycrystal silicon layer 4. The silicon oxide film 3 and the interlayer insulation film 5 which are formed on the upper portion of the n+type impurity region 2 and the polycrystal silicon layer 4 have respective parts thereof removed so as to connect the n+type impurity region 2 and the polycrystal silicon layer 4 with aluminum wiring electrodes 6a, 6b.

公开(公告)号：JPH09293686A

公开(公告)日：1997-11-11

申请号：JP10779896

申请日：1996-04-26

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L29/78 ,  H01L21/265

Abstract: PROBLEM TO BE SOLVED: To make it possible to form an optimum diffused region on a semiconductor substrate flexibly. SOLUTION: A resist pattern 2, wherein open parts 21 with the section, which is cut along the thickness direction and is formed into roughly a square form, are arranged regularly and repeatedly, is formed on the surface of a semiconductor substrate 1. Then, while the substrate 1 is rotated, impurity ions 3 are implanted in the surface of the substrate 1 from an angle of incidence set including at least a direction slanted to a perpendicular erected on the surface of the substrate 1 using the resist pattern 2 as a mask. Then, after the resist pattern 2 is removed, a heat treatment is performed to form an impurity ion 3 diffused region 32 in the substrate 1.

公开(公告)号：JPH08274066A

公开(公告)日：1996-10-18

申请号：JP7108895

申请日：1995-03-29

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE: To contrive to improve the reliability of a metal wiring which is formed in a contact window. CONSTITUTION: A BPSG film 9 formed on a semiconductor substrate 5 by a CVD method is heat-treated in an atmosphere containing phosphorus to form a heavily phosphorus doped region 10 on the side of the upper surface of the film 9 and at the same time, the film 10 is flattened, a contact window 12 to reach a second conductivity type semiconductor layer 7 is opened by dry etching using a resist pattern 11 as a mask and the parts of the sidewalls of the window 12 are overetched by wet etching. Accordingly, the window 12 can be easily formed into a roughly forward-tapered form with an opening spread in the side of its upper surface.

公开(公告)号：JPH06283527A

公开(公告)日：1994-10-07

申请号：JP6638493

申请日：1993-03-25

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/205 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L23/52

Abstract: PURPOSE:To avoid discontinuity of a wiring and prevent the wiring from becoming thive in a semiconductor device, wherein a multilayer wiring is formed. CONSTITUTION:A photoresist 21 is applied to a silicon oxide film 19 on a semiconductor substrate 17 and a pattern for opening contact parts 18a and a wiring part 18b is formed into two steps. Then, the film 19 at positions, wherein the parts 18 are opened, is etched to its middle and a photoresist 21a at a position, wherein the part 18b is opened, is etched until the photoresist 21a is eliminated. Then, the film 19 is evenly etched extending over the whole substrate 17 and a position for burying an aluminium wiring 18 is opened in the film 19. The resist 21 is removed and an aluminum film 25 is deposited by a CVD method. After an opening part of the wiring 18 is filled with the aluminum film 25, the aluminium film deposited on the parts other than the part 18b is etched away to form the wiring 18 and a multilayer interconnection is formed.

公开(公告)号：JPH06163663A

公开(公告)日：1994-06-10

申请号：JP31543492

申请日：1992-11-25

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/66

Abstract: PURPOSE:To evaluate the depth of a groove without destruction by forming the groove in a silicon substrate, using this part as the detector part for measuring the depth of the groove, providing evaluating trenches around the detector part, finding the distance from each detector part of the trench pattern where a seat part reaches the detector part, and performing computation. CONSTITUTION:After an oxide film 12 is formed on the surface of a silicon substrate 11, a photoresist pattern 13 is formed. Etching is formed, and a hole 14 is formed. Then, the photoresist pattern 13 is removed. With the oxide film 12 as a mask, a groove 16 is formed by anisotropic dry etching. Then, an evaluating detector part 17 is formed by anisortopic etching with alkai aqueous solution. The inlet port of the detector part 17 is narrow, and the inside becomes wider toward the middle part. Hole parts 9a to 9c for forming depth measuring trenches are formed around the detector parts 17 so that the distances from the detector parts are different. Etching is performed, and evaluating trenches 21a to 21c are formed. The trench 21f, whose bottom part reaches the detector part, and a distance DELTA2 are obtained, and D2 is obtained by D2=DELTA2tantheta.