公开(公告)号：DE69838101D1

公开(公告)日：2007-08-30

申请号：DE69838101

申请日：1998-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  FONTANA MARCO

IPC: G11C7/00 ,  G11C7/10

Abstract: A method for reading a memory, particularly a non-volatile memory, whose particularity is that it comprises the steps of: generating a memory enable signal (CE); generating a signal (ALE) for the visibility, inside the memory, of address signals generated externally with respect to the memory, the address signals being adapted to allow access to corresponding memory locations of the memory; generating a signal (RD) for the synchronous advancement of the read operation within the memory; each change of state of the memory enable signal (CE), together with a change of state of the address signals, being matched by different cycles for reading the memory, the different read cycles being enabled according to the state of the signal (ALE) for the visibility, inside the memory, of address signals generated externally to the memory, the logic state of the visibility signal switching between the high logic state, the low logic state and the pulsed state; emission of the data read from the memory being correlated to the state transition of the signal (RD) for the synchronous advancement of the reading of the memory.

公开(公告)号：ITTO20040470A1

公开(公告)日：2004-10-08

申请号：ITTO20040470

申请日：2004-07-08

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO

公开(公告)号：DE69632574D1

公开(公告)日：2004-07-01

申请号：DE69632574

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C5/02 ,  G11C16/28 ,  G11C16/06

公开(公告)号：DE69531823T2

公开(公告)日：2004-07-01

申请号：DE69531823

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

公开(公告)号：DE69632022D1

公开(公告)日：2004-05-06

申请号：DE69632022

申请日：1996-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/00

Abstract: A regulator circuit of the output voltage produced by a voltage boost circuit, able of generating a hysteretic control logic signal of said boost circuit, comprises a sensing branch comprising at least an inverting stage composed of an enhanced threshold load transistor of a first type of conductivity and a complementary natural transistor and a nonvolatile memory element functionally connected in series with said complementary inverting stage between the two supply nodes. A biasing branch, enabled by a start signal of said boost circuit, generates a first voltage, surely higher than the threshold voltage of said load transistor and a second voltage surely higher than the threshold voltage of said natural transistor. Means enabled by said start signal apply to a control terminal of said nonvolatile memory element a voltage representative of the regulated output voltage produced by said boost circuit. One or more inverters are coupled in cascade to said inverting stage to produce the required logic signal.

公开(公告)号：DE69631242D1

公开(公告)日：2004-02-05

申请号：DE69631242

申请日：1996-04-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/00

公开(公告)号：DE69626099T2

公开(公告)日：2003-11-27

申请号：DE69626099

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/06 ,  G11C16/28

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure (2) that has two output nodes (OUT-L, OUT-R) and has the particularity that it comprises an equalization transistor (7) of a first polarity that is adapted to equalize the two output nodes (OUT-L, OUT-R) and is connected between a first branch (8) and a second branch (9), in which the output nodes are arranged; the equalization transistor (7) is driven by an equalization signal (EQ) whose slope can be modulated as a function of the conductivity of the memory cell of the memory device involved in the reading operation.

公开(公告)号：DE69625582T2

公开(公告)日：2003-11-20

申请号：DE69625582

申请日：1996-03-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO

IPC: G11C7/10 ,  G11C7/00

Abstract: A non-volatile memory device (1) having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus (3) that runs from one end of the memory device to the other, one or more source structures (5', 5'') that lie externally and internally to the memory device (1), and timer means (8); the timer means (8) are adapted to time-control the independent and exclusive access of the external and internal source structures (5', 5''), within a same memory cycle, to the internal bus (3) for the transmission of data, controls, and functions, from one end of the memory (1) to the other over the internal bus (3).

公开(公告)号：DE69626625T2

公开(公告)日：2003-10-02

申请号：DE69626625

申请日：1996-04-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C29/00 ,  G11C29/44 ,  G06F11/00

Abstract: A method for detecting redunded defective addresses in a memory device with redundancy comprising at least one memory register (RR1-RRn;RR1'-RRn') for storing at least one defective address. The memory register comprises a plurality of memory units (MU0-MU10) each one storing a defective address bit and comparing the defective address bit with a respective current address bit (A0-A10) supplied to the memory device; the memory register activates a respective redundancy selection signal (RS1-RSn;RSA1-RSAn,RSB1-RSBn) when the current address coincides with the defective address stored therein. The method provides for: activating a forcing signal (F) for forcing the activation of the redundancy selection signal to be independent of the coincindence of a first group (A0-A3) of current address bits, associated to a respective first group (G2) of the memory units, with the defective address bits stored in the respective first group (G2) of memory units; scanning all the possible configurations of a second group (A4-A10) of current address bits associated to a second group (G1) of the memory units and sequentially supplying the memory device with all the configurations; detecting a configuration of the second group (A4-A10) of current address bits for which the redundancy selection signal is activated; while supplying the memory device with the configuration of the second group (A4-A10) of current address bits, deactivating the forcing signal and sequentially supplying the memory device with a scanning of all the possible configurations of the first group (A0-A3) of address bits; detecting a configuration of the first group (A0-A3) of current address bits for which the redundancy selection signal is activated.

公开(公告)号：IT1318978B1

公开(公告)日：2003-09-19

申请号：ITMI20002163

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/10 ,  G11C16/26 ,  G11C16/32

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon transitions of the second type, and a fourth circuit controlled by the first circuit to supply a stimulus signal to a timing circuit of the memory, the stimulus signal corresponding to the first synchronism signal for a random-access reading, or to the second synchronism signal for a sequential reading.