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    1.
    发明专利
    未知

    公开(公告)号：DE69531823D1

    公开(公告)日：2003-10-30

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    4.
    发明专利
    未知

    公开(公告)号：DE69838101D1

    公开(公告)日：2007-08-30

    申请号：DE69838101

    申请日：1998-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  FONTANA MARCO

    IPC: G11C7/00 ,  G11C7/10

    Abstract: A method for reading a memory, particularly a non-volatile memory, whose particularity is that it comprises the steps of: generating a memory enable signal (CE); generating a signal (ALE) for the visibility, inside the memory, of address signals generated externally with respect to the memory, the address signals being adapted to allow access to corresponding memory locations of the memory; generating a signal (RD) for the synchronous advancement of the read operation within the memory; each change of state of the memory enable signal (CE), together with a change of state of the address signals, being matched by different cycles for reading the memory, the different read cycles being enabled according to the state of the signal (ALE) for the visibility, inside the memory, of address signals generated externally to the memory, the logic state of the visibility signal switching between the high logic state, the low logic state and the pulsed state; emission of the data read from the memory being correlated to the state transition of the signal (RD) for the synchronous advancement of the reading of the memory.

    5.
    发明专利
    未知

    公开(公告)号：DE69531823T2

    公开(公告)日：2004-07-01

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    7.
    发明专利
    未知

    公开(公告)号：DE69628908D1

    公开(公告)日：2003-08-07

    申请号：DE69628908

    申请日：1996-04-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  FONTANA MARCO

    IPC: G11C16/30 ,  G11C5/14 ,  G11C16/06

    Abstract: The present invention relates to a voltage regulator (1) for the programming of electrically programmable non-volatile memory cells in a cells matrix divided in segments with said regulator being the type comprising an amplifier stage (2) connected and powered between a first (Vpp) and a second reference voltage (GND) and having: a first input terminal (+) connected to a divider (3) of the first reference voltage (Vpp), an output terminal (U) connected to the control terminal of a MOS transistor (Mu) which has a conduction terminal connected to the memory cells through a programming line (6), a second input terminal (-) connected in feedback to said programming line (6), and an input circuit portion (8) made up of active elements and inserted in turn between said reference voltages (Vpp,GND). This portion (8) is active on the connection between the amplifier (2) and the first reference voltage (Vpp) in response to at least one pair of signals (PG,DI) to activate the regulator only when there is at least one cell to be programmed in the segment associated with the regulator. Specifically, the above mentioned input circuit portion (8) is made up of a complementary pair of transistors (Pin,Min) and at least one enablement transistor (M2) with there being applied to the complementary pair a first programming enablement signal (PG) and to the transistor (M2) there being applied a second signal (DI) indicating the presence of a bit to be programmed.

    9.
    发明专利
    未知

    公开(公告)号：DE69619501D1

    公开(公告)日：2002-04-04

    申请号：DE69619501

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

    IPC: G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G06F11/20

    Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells, which has the particularity that it comprises: at least one bidirectional internal bus (1) for the transfer of data from and to the memory; a redundancy management line (2) that is associated with the internal bus (1); means (8) for enabling/disabling the transmission, over the internal bus (1), of the data from the memory toward the outside; means (11) for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and the redundancy line (2) during the reading of the memory matrix and during its programming.

    10.
    发明专利
    未知

    公开(公告)号：ITTO20010537D0

    公开(公告)日：2001-06-05

    申请号：ITTO20010537

    申请日：2001-06-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FONTANA MARCO ,  PAGLIATO MAURO ,  ROLANDO PAOLO ,  ODDONE GIORGIO

    IPC: H02M3/07

    Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

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