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    SENSE AMPLIFIER WITH HYSTERESIS
    1.
    发明专利
    SENSE AMPLIFIER WITH HYSTERESIS 失效

    公开(公告)号：JPH07312092A

    公开(公告)日：1995-11-28

    申请号：JP13588495

    申请日：1995-05-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARCELLA ANTONIO

    IPC: G11C17/00 ,  G11C7/06 ,  G11C16/06

    Abstract: PURPOSE: To ensure noise immunity, and to inhibit the occurrence of spurious output transition by connecting an inverting amplifying stage formed by a single transistor between the output node of a differential input stage and an intermediate node thereof. CONSTITUTION: When an output at a differential stage is under a high state, a transistor M8 is tuned on, and switches an output level from the high state to a low state. On the other hand, the gate voltage of the transistor coincides with a voltage drop crossing a transistor M5. The transistor M2 of forward feedback is conducted at the time of the high state of the output at the differential stage. A transistor M9 can flow a sufficient current for the generation of the turn-off of the transistor M8 by beforehand specifying the dimensions of the transistors M2, M5, M8 at that time. Accordingly, noise immunity is ensured, and the occurrence of spurious output transition can be suppressed.

    READ-OUT METHOD FOR NON-VOLATILE MEMORY CELL AND SENSE AMPLIFIER FOR NON-VOLATILE MEMORY CELL
    2.
    发明专利
    READ-OUT METHOD FOR NON-VOLATILE MEMORY CELL AND SENSE AMPLIFIER FOR NON-VOLATILE MEMORY CELL 失效

    公开(公告)号：JP2001014875A

    公开(公告)日：2001-01-19

    申请号：JP2000182753

    申请日：2000-06-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARCELLA ANTONIO ,  ROLANDI PAOLO

    IPC: G11C16/02 ,  G11C16/06 ,  G11C16/28

    Abstract: PROBLEM TO BE SOLVED: To realize a read-out system for a memory cell the detection ratio of which depends on read-out voltage. SOLUTION: This method has a first process in which a memory cell 2 of a memory matrix 3 is selected by a row decoder 5 and a column multiplexer 4, a second process in which voltage on a drain electrode of a selected memory cell P2 is pre-loaded so as to reach a previously prescribed value and equalization processing is performed, and a third process in which a selected memory cell P2 is read out with a detection ratio depending on read-out voltage of this memory cell.

    3.
    发明专利
    未知

    公开(公告)号：DE69619501D1

    公开(公告)日：2002-04-04

    申请号：DE69619501

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

    IPC: G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G06F11/20

    Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells, which has the particularity that it comprises: at least one bidirectional internal bus (1) for the transfer of data from and to the memory; a redundancy management line (2) that is associated with the internal bus (1); means (8) for enabling/disabling the transmission, over the internal bus (1), of the data from the memory toward the outside; means (11) for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and the redundancy line (2) during the reading of the memory matrix and during its programming.

    4.
    发明专利
    未知

    公开(公告)号：DE69633774D1

    公开(公告)日：2004-12-09

    申请号：DE69633774

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  FONTANA MARCO ,  BARCELLA ANTONIO

    IPC: G11C16/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/00

    Abstract: A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, characterized in that the memory is divided into at least two memory half-matrices that are arranged on different half-planes, and in that the circuit comprises, for each one of the at least two memory half-matrices, a reference unit (3i) for each one of the at least two memory half-matrices and an associated unit (4) for reproducing the propagation of the signals along the reference unit, the reference unit (3i) and the associated propagation reproduction unit (4) having a structure that is identical to each generic word line of the memory device, the reference and propagation reproduction units of one of the at least two memory half-matrices being activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit (4), the conditions for starting correct and certain reading of the selected memory cell.

    5.
    发明专利
    未知

    公开(公告)号：DE69721724T2

    公开(公告)日：2004-03-25

    申请号：DE69721724

    申请日：1997-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FONTANA MARCO ,  BARCELLA ANTONIO

    IPC: G11C8/08 ,  G11C16/12 ,  G11C16/06 ,  G11C8/00

    Abstract: In a first operation mode the level shifter (36) transmits as output a logic input signal (Si) and in a second operation mode it shifts the high logic level of the input signal from a low (Vdd) to a high voltage (Vpp). The level shifter comprises a CMOS switch (42) and a pull-up transistor (43); the CMOS switch (42) comprises an NMOS transistor (45) and a PMOS transistor (44) which are connected in parallel between the input (37) and the output (39) of the shifter and have respective control terminals connected to a first supply line (4) at low voltage (Vdd) and, respectively, to a control line (46) connected to ground in the first operation mode and to the high voltage (Vpp) in the second operation mode; the pull-up transistor (43) is connected between the output (39) of the shifter and a second supply line (2) switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line (4).

    6.
    发明专利
    未知

    公开(公告)号：DE69531823D1

    公开(公告)日：2003-10-30

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

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