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258 records (took 0.033 seconds)

    92.
    发明专利
    未知

    公开(公告)号：ITMI962210A1

    公开(公告)日：1998-04-25

    申请号：ITMI962210

    申请日：1996-10-25

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI

    IPC: H03K3/356 ,  H03K17/693

    Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

    94.
    发明专利
    未知

    公开(公告)号：DE69312305T2

    公开(公告)日：1998-01-15

    申请号：DE69312305

    申请日：1993-12-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07

    Abstract: A voltage booster (1) comprising a charge pump (2) for generating a boost voltage (Vboost) over a boost line (3). The booster comprises a comparator (6) which is supplied by a voltage divider (5) with a voltage V1 proportional to the boost voltage (Vboost), and by a reference source (4) with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump (2). A voltage limiter (8) is connected between the boost line (3) and ground; and a boost circuit (7) accelerates the voltage increase on the boost line following low-power operation in which the paths toward ground are interrupted for reducing consumption.

    95.
    发明专利
    未知

    公开(公告)号：DE69220632T2

    公开(公告)日：1998-01-02

    申请号：DE69220632

    申请日：1992-08-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22

    Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

    96.
    发明专利
    未知

    公开(公告)号：DE69115952D1

    公开(公告)日：1996-02-15

    申请号：DE69115952

    申请日：1991-02-07

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18

    Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCCmax. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

    97.
    发明专利
    未知

    公开(公告)号：DE68912979T2

    公开(公告)日：1994-05-19

    申请号：DE68912979

    申请日：1989-06-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  G11C5/00 ,  G11C17/00 ,  G11C16/06

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

    98.
    发明专利
    未知

    公开(公告)号：DE68912979D1

    公开(公告)日：1994-03-24

    申请号：DE68912979

    申请日：1989-06-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  G11C5/00 ,  G11C17/00 ,  G11C16/06

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

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