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    Synchronous counter for electronic memories
    91.
    发明公开
    Synchronous counter for electronic memories 有权
    SynchronerZählerfürelektronische Speicher

    公开(公告)号：EP1126467A1

    公开(公告)日：2001-08-22

    申请号：EP00830100.4

    申请日：2000-02-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi

    IPC: G11C8/04 ,  G11C7/10 ,  H03K23/66

    CPC classification number: H03K23/665 ,  G11C7/1018 ,  G11C8/04

    Abstract: A memory counter circuit, comprising a plurality of mutually connected counter stages (1a, 1), comprising:

    an internal address bus (2) which is interfaced with each one of the counter stages (1a, 1) and is adapted to send an external address signal (18) to each one of the counter stages;
    means (19, 20) for loading the external address signal (18) onto the internal address bus (2);
    means (3) for enabling the connection between the internal bus (2) and each one of the counter stages (1a, 1), the means being driven by a true address latch enable signal (ALE);
    means (15) for generating the true address latch enable signal (ALE) starting from an external address latch signal (16) and a fast address latch enable signal (ALE-fast) which is adapted to drive the means (19, 20) for loading the external address (18) onto the internal address bus (2); and
    means (21) for generating clock signals (M-inc, S-inc) for synchronizing each one of the counter stages (1a, 1), the synchronization signals not being simultaneously active.

    Abstract translation: 一种存储器计数器电路，包括多个相互连接的计数器级（1a，1），包括：内部地址总线（2），其与每个所述计数器级（1a，1）接口，并且适于发送外部 地址信号（18）到每个所述计数器级; 用于将外部地址信号（18）加载到内部地址总线（2）上的装置（19,20）; 用于启用内部总线（2）和每个计数器级（1a，1）之间的连接的装置（3），该装置由真实的地址锁存使能信号（ALE）驱动; 用于从外部地址锁存信号（16）开始产生真实地址锁存使能信号（ALE）的装置（15）和适于驱动装置（19,20）的快速地址锁存使能信号（ALE-fast） 将外部地址（18）加载到内部地址总线（2）上; 以及用于产生用于同步每个所述计数器级（1a，1）的时钟信号（M-inc，S-inc）的装置（21），所述同步信号不是同时有效。

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