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    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
    3.
    发明公开
    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit 审中-公开
    从交错突发存储器和相应的电路的控制协议的地址释放信号（ALE）的内部再生

    公开(公告)号：EP1122733A1

    公开(公告)日：2001-08-08

    申请号：EP00200752.4

    申请日：2000-03-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Campanale, Fabrizio ,  De Ambroggi, Luca Giuseppe ,  Pascucci, Luigi

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An interleaved memory readable in sequential access synchronous mode and in random access asynchronous mode, in function of external protocol signals ( ALE; CEn, RD ), has a circuit of internal regeneration of an external input address latch enabling signal ( ALE ), filtered by a second external chip enable signal ( CEn ). The circuit comprises a latch ( LATCH ) storing the external signal ( ALE_EXT ) of input address latch enabling and a NOR gate combining the output ( ALE_BUFF ) of the latch with the second external signal of chip enable ( CEn ) and producing a first internal replica signal of address latch enabling ( ALE_FAST ). Delay circuits in cascade to the output of the latch and in cascade of the input pad of the external signal of chip enable ( CEn ) and logic means combining the internally generated replica signal ( ALE_FAST ) and the signal ( ALE_BUFF ) present at the output of the latch with signals retarded by said delay circuits produce set and reset signals of an output flip-flop outputting a second internally generated reconditioned address latch enabling signal ( ALE ). The reconditioned signal has a raising edge conditionally retarded compared to the raising edge of the external command ( ALE_EXT ) and a duration that is conditionally incremented such to compensate for eventual critical asynchronisms between the two protocol external signals ( ALE_EXT, CEn ) in the different modes of operation of the interleaved memory.

    Abstract translation: 一种交错的存储器可读在顺序访问同步模式和在随机存取异步模式下，在外部协议信号的功能（ALE; CEN，RD）具有外部输入地址锁存器的内部再生的电路启动信号（ALE），通过过滤 第二外部芯片使能信号（CEN）。 该电路包括一个锁存器（LATCH）存储输入地址锁存器的外部信号（ALE_EXT）启用和NOR门的锁存器的输出（ALE_BUFF）相结合的芯片使能（CEN）的第二外部信号，并产生第一内部复制品 地址的信号锁存启用（ALE_FAST）。 在级联延迟电路的锁存器的输出和在芯片的外部信号的输入焊盘的级联使能（CEN）和逻辑装置组合所述内部生成的复制信号（ALE_FAST）和信号（ALE_BUFF）存在的输出 与由所述延迟电路延迟的锁存信号产生置位和复位的输出触发器输出婷第二内部产生的修复地址锁存使能信号（ALE）的信号。 该翻新信号具有上升沿有条件延迟相比于外部命令（ALE_EXT）的上升沿和一个持续时间没有条件指针累加寻求以补偿不同的模式这两种协议的外部信号（ALE_EXT，CEN）之间最终临界异步性 的交错存储器的操作。

    Accelerated carry generation.
    5.
    发明公开
    Accelerated carry generation. 审中-公开
    加速携带生成。

    公开(公告)号：EP1122739A2

    公开(公告)日：2001-08-08

    申请号：EP00830312.5

    申请日：2000-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Ambroggi, Luca Giuseppe ,  Kumar, Promod ,  Campanale, Fabrizio ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Condemi, Carmelo

    IPC: G11C7/10 ,  G06F7/50

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An address binary counter for a subdivision bank of the cell array of an interleaved memory with burst access enabled by an enabling signal (ENABLE), comprises as many stages as the bits that may be stored in the cells of a row of the bank and a carry calculation network.
    The carry calculation network comprises an ordered group of independent carry generators, each of a certain number of stages, and having its own enabling bit, that are input with a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit.
    The enabling bit of the first carry generator of the ordered group is said enabling signal (ENABLE), and the enabling bit of any other carry generator of the ordered group is the logic AND of said enabling signal and of the input bits of the preceding carry generator of the ordered group.

    Abstract translation: 用于具有通过使能信号（ENABLE）启用的突发访问的交织存储器的单元阵列的细分阵列的地址二进制计数器包括与可以存储在该阵列的一行的单元中的比特以及与 携带计算网络。 进位计算网络包括一组有序的独立进位发生器，每一级具有一定数量的级，并且具有其自己的使能位，输入级的数量等于级数， 有条不紊地从最低位开始。 有序组的第一进位发生器的使能位是所述使能信号（ENABLE），并且有序组的任何其他进位发生器的使能位是所述使能信号和先前进位的输入位的逻辑与 有序组的生成器。

    Circuit for managing the transfer of data streams from a plurality of sources within a system
    7.
    发明公开
    Circuit for managing the transfer of data streams from a plurality of sources within a system 审中-公开
    Schallung zur Steuerung vonDatenströmenübertragungaus mehrerer Quellen eines Systems

    公开(公告)号：EP1122737A1

    公开(公告)日：2001-08-08

    申请号：EP00830364.6

    申请日：2000-05-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomaiuolo, Francesco ,  Campanale, Fabrizio ,  Nicosia, Salvatore ,  De Ambroggi, Luca Giuseppe ,  Kumar, Promod

    IPC: G11C7/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: The transfer of data within a system having a plurality of data sources (ASYNC BLOCK asynchronous and/or having different bitrates, to produce an output data stream (OUT) synchronous with a certain external timing signal (CLOCK, RD) of request of updating of the datum currently present at the output, is managed by a circuit that includes an output register (OUT REG) in which the datum to be made available at the output is stored and at least an output buffer (OUT BUFF) driving an external data line and functionally coupled to the output of said output register (OUT REG). Each data source (ASYN_BLOCK ) has a data loading register (REG ), a selection multiplexer (MUX) of data to be transferred from one or another of said loading registers to said output register (OUT REG). A central control unit (CPU) produces a plurality of control signals (START , REQ , PRIORITY , CLOCK, RD, GLOBAL_RESET). The circuit managing the transfer (SYNC_ASYN CONTROL) includes a plurality of identical circuits, each dedicated to one of said data sources and composed of a coincidence detecting circuit with hooking (COINCIDENCE DETECTOR WITH HOOKING) input with the logic end signal (PULSE) of said external timing signal (CLOCK RD) and of a selection signal (REQ ) of the source of the datum to be produced in output, and a confirmation signal (DATA_READY ) of availability of the datum at the output of said selected source, outputting in a stretching signal (OK_STR), and of a conditioned update path of the output datum constituted by a first bistable circuit (LATCH UPDATE FLAG) set by the inverted confirmation signal (DATA_READY ) and reset by the logic OR of a global reset command (GLOBAL_RESET) generated by the central control unit (CPU) and of the logic OR of the timing signal (CLOCK) and of the stretching signal (OK_STR), outputting a first flag (OK_UPDATE) of enablement of the updating; a second bistable circuit (ENABLING FLAG OF OUT REG UPDATE) set by the output of said detecting circuit and reset by the logic OR of the signal (GLOBAL_RESET) and of a signal (NEW_OUT) corresponding to the logic OR of signals (NEW_OUT ) coming from the respective data sources , outputting an update flag (PRE_LOAD); a logic OR gate, input with the update flag (PRE-LOAD) and with the logic OR signal of the signal (PULSE) and of the stretching signal (OK_STR) and producing in output a selection signal (LOAD ) for the multiplexer (MUX); a pass-gate coupling the input of an output buffer OUT BUFF to the respective output register OUT REG, enabled by the logic OR signal (NEW_OUT) of the signals (NEW_OUT ), each corresponding to the logic OR of the signal (PULSE) and of the stretching signal (OK_STR) of the managing circuit (block ) of a respective data source.

    Abstract translation: 具有异步和/或具有不同比特率的多个数据源（ASYNC BLOCK <1：n>）的系统内的数据传送，以产生与某个外部定时信号（CLOCK，RD）同步的输出数据流（OUT） 更新当前存在于输出端的数据的请求由包括输出寄存器（OUT REG）的电路管理，其中存储在输出端可用的数据，并且至少输出缓冲器（OUT BUFF） 每个数据源（ASYN_BLOCK <1：n>）都有一个数据加载寄存器（RE​​G <1：n>），一个选择多路复用器（MUX） ）从一个或另一个所述加载寄存器传送到所述输出寄存器（OUT REG）的数据，中央控制单元（CPU）产生多个控制信号（START <1：n>，REQ <1：n> ，优先，CLOCK，RD，GLOBAL_RESET）。管理传输的电路（SYNC_ASYN CONTROL）包括多个 每个专用于所述数据源中的一个，并由具有与所述外部定时信号（CLOCK RD）的逻辑结束信号（PULSE））和选择信号（PORSE）一起输入的具有挂钩（具有HOOKING的COINCIDENCE检测器）的符合检测电路组成 （REQ i），以及在所述选择的源的输出处的数据的可用性的确认信号（DATA_READY ），以拉伸信号（OK_STR）输出， 以及由由反相确认信号（DATA_READY i）设置的第一双稳态电路（LATCH UPDATE FLAG）构成的输出数据的调节更新路径，并由由所述反相确认信号（DATA_READY）产生的全局复位命令（GLOBAL_RESET）的逻辑OR复位 中央控制单元（CPU）和定时信号（CLOCK）和拉伸信号（OK_STR）的逻辑或运算，输出启动更新的第一标志（OK_UPDATE）; 由所述检测电路的输出设置的第二双稳态电路（ENABLING FLAG OF OUT REG UPDATE），并由信号（GLOBAL_RESET）的逻辑或与信号（NEW_OUT ），输出更新标志（PRE_LOAD）; 逻辑或门，用更新标志（PRE-LOAD）和信号（PULSE）的逻辑或信号和拉伸信号（OK_STR）输入，并在输出中产生选择信号（LOAD ），用于 多路复用器（MUX）; 将输出缓冲器OUT BUFF的输入耦合到各个输出寄存器OUT REG的通过门，该寄存器通过信号（NEW_OUT i）的逻辑“或”信号（NEW_OUT）使能，每个对应于信号的逻辑或 PULSE）和相应数据源的管理电路（块i）的拉伸信号（OK_STR）。

    Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
    8.
    发明公开
    Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data 有权
    用于输出读出的数据交错的数据路径和交织存储器输出控制体系结构，以及脉冲发生器

    公开(公告)号：EP1122735A1

    公开(公告)日：2001-08-08

    申请号：EP00830291.1

    申请日：2000-04-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicosia, Salvatore ,  Campanale, Fabrizio ,  Kumar, Promod ,  De Ambroggi, Luca Giuseppe ,  Tomaiuolo, Francesco

    IPC: G11C7/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An interleaved data path and output management architecture for an interleaved memory, divided in at least a first bank and a second bank (EVEN BANK, ODD BANK) , each provided with an array of sense amplifiers (EVEN SENSE, ODD SENSE) and a register of read data (DATA OD REGISTER, DATA EV REGISTER) , and comprising an array of output buffers ( BUFFOUT) , controlled by external protocol signals (CE, OE) and a control and timing circuitry (TIMING) receiving as input external protocol signals (ALE, RD, CE) and producing enabling and/or path selection signals ( SAEN_EVEN, SAEN_ODD, SAlatch_EVEN, SAlatch_ODD, LOAD_EVEN, LOAD_ODD) , comprises:

    at least a third register (DATA OUT REGISTER) to the inputs of which are fed the output data of said registers of data read from the two banks DATA EV REGISTER, DATA OD REGISTER) in function of path selection signals (LOAD_EVEN, LOAD_ODD) produced by said control and timing circuitry (TIMING) ; and
    an array of pass-gates controlled in common by a control signal (DLATCHN) generated by said control and timing circuitry b enabling the transfer of data stored in said third register (DATA OUT REGISTER) to respective inputs of said array of output buffers (BUFFOUT).

    Abstract translation: 用于在交织存储器的交错数据路径和输出管理体系结构，划分成至少第一组和第二行（EVEN BANK，ODD BANK），分别设置有在读出放大器的阵列（EVEN SENSE，ODD SENSE）和寄存器 的读接收作为输入的外部协议信号数据（DATA REGISTER OD DATA REGISTER EV），以及输出缓冲器阵列，其包含（BUFFOUT），由外部协议信号（CE，OE）和一个控制和定时电路（定时）进行控制（ ALE，RD，CE）和允许生产和/或路径选择信号（SAEN_EVEN，SAEN_ODD，SAlatch_EVEN，SAlatch_ODD，LOAD_EVEN，LOAD_ODD）包括：至少一第三寄存器（DATA REGISTER OUT）至哪个的馈送输出的输入 所述（在路径选择信号（LOAD_EVEN，LOAD_ODD的功能）由所述控制和定时电路产生的定时）从两家银行DATA EV寄存器数据OD寄存器）读取的数据的寄存器的数据; （以及由所述控制和定时电路产生的b使得存储在所述第三寄存器（DATA REGISTER OUT数据的传送的控制信号（DLATCHN）在共同控制的通门阵列）来respectivement输出缓冲器的所述阵列的输入 BUFFOUT）。

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