公开(公告)号：US20090026559A1

公开(公告)日：2009-01-29

申请号：US11781470

申请日：2007-07-23

Applicant: James F. Detry

Inventor： James F. Detry

IPC: H01L29/84 ,  H01L21/20

CPC classification number: B81C1/00595 ,  B81C1/00365 ,  B81C2201/0136 ,  B81C2201/0167 ,  B81C2203/031

Abstract: A wafer for use in a MEMS device having two doped layers surrounding an undoped layer of silicon is described. By providing two doped layers around an undoped core, the stress in the lattice structure of the silicon is reduced as compared to a solidly doped layer. Thus, problems associated with warping and bowing are reduced. The wafer may have a pattered oxide layer to pattern the deep reactive ion etch. A first deep reactive ion etch creates trenches in the layers. The walls of the trenches are doped with boron atoms. A second deep reactive ion etch removes the bottom walls of the trenches. The wafer is separated from the silicon substrate and bonded to at least one glass wafer.

Abstract translation: 描述了一种用于具有围绕未掺杂硅层的两个掺杂层的MEMS器件的晶片。 通过在未掺杂的芯周围提供两个掺杂层，与固体掺杂层相比，硅的晶格结构中的应力降低。 因此，与翘曲和弯曲相关的问题减少。 晶片可以具有图案化的氧化物层以对深层反应离子蚀刻进行图案化。 第一深反应离子蚀刻在层中产生沟槽。 沟槽的壁掺杂有硼原子。 第二次深反应离子蚀刻去除沟槽的底壁。 将晶片与硅衬底分离并结合至至少一个玻璃晶片。

公开(公告)号：US20080233752A1

公开(公告)日：2008-09-25

申请号：US11927810

申请日：2007-10-30

Applicant: Sang-Choon KO ,  Chi-Hoon JUN ,  Hyeon-Bong PYO ,  Seon-Hee PARK

Inventor： Sang-Choon KO ,  Chi-Hoon JUN ,  Hyeon-Bong PYO ,  Seon-Hee PARK

IPC: H01L21/306

CPC classification number: B81C1/00801 ,  B81C2201/0133 ,  B81C2201/0136

Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

Abstract translation: 提供了一种用于制造MEMS的浮动结构的方法。 一种用于制造微机电系统（MEMS）的浮动结构的方法，包括以下步骤：a）在衬底上形成包含掺杂有杂质的薄层图案的牺牲层; b）在牺牲层上形成支撑层; c）通过使用随后的方法形成浮在支撑层上的结构; d）形成暴露薄层图案的两侧部分的蚀刻孔; 以及e）通过所述蚀刻孔去除所述牺牲层，以在所述支撑层和所述基底之间形成气隙。

公开(公告)号：US07255800B1

公开(公告)日：2007-08-14

申请号：US10710984

申请日：2004-08-16

Applicant: Shekhar Bhansali ,  Abdu Rub Abdur ,  Sunny Kedia

Inventor： Shekhar Bhansali ,  Abdu Rub Abdur ,  Sunny Kedia

IPC: B44C1/22

CPC classification number: B81C1/005 ,  B81B2203/0353 ,  B81C1/00619 ,  B81C2201/0115 ,  B81C2201/0133 ,  B81C2201/0136 ,  H01L21/02052 ,  H01L21/3063

Abstract: The present invention illustrates a bulk silicon etching technique that yields straight sidewalls, through wafer structures in very short times using standard silicon wet etching techniques. The method of the present invention employs selective porous silicon formation and dissolution to create high aspect ratio structures with straight sidewalls for through wafer MEMS processing.

Abstract translation: 本发明示出了使用标准硅湿式蚀刻技术在非常短的时间内通过晶片结构产生直的侧壁的体硅蚀刻技术。 本发明的方法采用选择性多孔硅形成和溶解以产生具有用于晶片MEMS加工的直侧壁的高纵横比结构。

公开(公告)号：US20060141398A1

公开(公告)日：2006-06-29

申请号：US11276320

申请日：2006-02-24

Applicant: Noriyuki Shimoji ,  Masaki Takaoka

Inventor： Noriyuki Shimoji ,  Masaki Takaoka

IPC: G03F7/00

CPC classification number: F04B43/043 ,  B81B2203/0353 ,  B81C1/00626 ,  B81C2201/0136 ,  H01L29/0657

Abstract: A method of producing a semiconductor device is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.

Abstract translation: 公开了一种制造半导体器件的方法，其中在半导体衬底的上表面中形成有从其下表面的通孔，并且所需尺寸的开口形成在所述半导体衬底的上表面上的期望位置 基质。 在半导体衬底中形成用作蚀刻阻挡层的引导件。 在导向件中形成宽度为W 2的开口。 开口面向形成通孔所使用的掩模中的开口，其宽度W 2比掩模中的开口的宽度W 4窄。 蚀刻进行的方向由蚀刻形成在导向器中的开口控制，从基板的下表面传导到基板的上表面，因此宽度W 1和上部开口的位置的偏差 可以控制基板的表面。

公开(公告)号：US20040266050A1

公开(公告)日：2004-12-30

申请号：US10486182

申请日：2004-08-20

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schafer

IPC: H01L021/00

CPC classification number: B81C1/00182 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

公开(公告)号：US06824960B2

公开(公告)日：2004-11-30

申请号：US10373235

申请日：2003-02-24

Applicant: In-Yao Lee ,  Chih-Ching Chen

Inventor： In-Yao Lee ,  Chih-Ching Chen

IPC: G03C500

CPC classification number: B81C1/0042 ,  B01L3/0241 ,  B41J2/16 ,  B41J2/1629 ,  B41J2/1631 ,  B81B2201/052 ,  B81B2203/0392 ,  B81C1/00595 ,  B81C2201/0136

Abstract: A method of manufacturing a fluid injection device. The method of the present invention applies a compensated geometric shape of the unetched isolating portions to increase the additional compensated portion for etching, or the ion implanting process to reduce the etching rate of the unetched isolating portions. Thus, crosstalk or overshoot in the isolating portions of the fluid injection device can be reduced, and the fluid injection device can be precisely manufactured in a small size.

Abstract translation: 一种制造流体注射装置的方法。 本发明的方法应用未蚀刻绝缘部分的补偿几何形状以增加用于蚀刻的附加补偿部分，或离子注入工艺以降低未蚀刻绝缘部分的蚀刻速率。 因此，可以减少流体注入装置的隔离部分中的串扰或过冲，并且能够精确地制造流体注射装置。

公开(公告)号：US06759265B2

公开(公告)日：2004-07-06

申请号：US10268711

申请日：2002-10-10

Applicant: Hans Artmann ,  Thorsten Pannek

Inventor： Hans Artmann ,  Thorsten Pannek

IPC: H01L2100

CPC classification number: B81C1/0069 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0139

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract translation: 在制造具有半导体材料基板的隔膜传感器单元的方法中，产生用于形成用于至少一个传感器的传感器元件结构的隔膜下方的平坦隔膜和隔热绝缘孔。 由限定传感器元件结构的特定区域中的由半导体材料制成的衬底接收与周围半导体材料的故意不同的掺杂，多孔半导体材料是由掺杂区域之间的半导体材料部分和半导体材料 在半导体中的阱区域被多孔化并且在传感器元件结构的部分被去除和/或变得多孔的情况下。

公开(公告)号：US20040053507A1

公开(公告)日：2004-03-18

申请号：US10651051

申请日：2003-08-29

Applicant: FUJITSU LIMITED

Inventor： Shoji Okuda ,  Hiroshi Tokunaga ,  Osamu Tsuboi

IPC: H01L021/461

CPC classification number: B81C1/0019 ,  B81B2201/0271 ,  B81C2201/0136 ,  B81C2201/019

Abstract: The method for fabricating a micro machine comprises the step of burying an oxide film 54 in a first semiconductor substrate 6, the step of bonding the first semiconductor substrate to the second semiconductor substrate with an insulation film 18 therebetween, the step of forming a first mask 66 with an opening in a first region and a second region on both sides of the first region, the step of etching the first semiconductor substrate with a first mask 66 and an oxide film 54 as a mask to thereby form a spring portion 20a integral with the first semiconductor substrate between the oxide film and the insulation film to thereby form a torsion bar including the spring portion, the step of forming a second mask 74 with an opening in the first region and the second region, the step of etching the second semiconductor substrate by using the second mask 74, and the step of etching the insulation film 18 in the first region and the second region. The thickness of the torsion bar can be easily controlled. Thus, a micro machine having a torsion bar can be fabricated with high yields.

Abstract translation: 微机的制造方法包括在第一半导体基板6中埋入氧化膜54的步骤，将第一半导体基板与绝缘膜18接合在第二半导体基板上的工序，形成第一掩模 66，其在第一区域的开口和第一区域两侧的第二区域，用第一掩模66和氧化物膜54作为掩模蚀刻第一半导体衬底的步骤，从而形成与 在所述氧化膜和所述绝缘膜之间的第一半导体衬底，从而形成包括所述弹簧部分的扭杆，在所述第一区域和所述第二区域中形成具有开口的第二掩模74的步骤，蚀刻所述第二半导体 通过使用第二掩模74的衬底以及蚀刻第一区域和第二区域中的绝缘膜18的步骤。 可以容易地控制扭杆的厚度。 因此，可以以高产率制造具有扭杆的微型机器。

公开(公告)号：US20030110867A1

公开(公告)日：2003-06-19

申请号：US10268711

申请日：2002-10-10

Inventor： Hans Artmann ,  Thorsten Pannek

IPC: G01F001/56

CPC classification number: B81C1/0069 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0139

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract translation: 在制造具有半导体材料基板的隔膜传感器单元的方法中，产生用于形成用于至少一个传感器的传感器元件结构的隔膜下方的平坦隔膜和隔热绝缘孔。 由限定传感器元件结构的特定区域中的由半导体材料制成的衬底接收与周围半导体材料的故意不同的掺杂，多孔半导体材料是由掺杂区域之间的半导体材料部分和半导体材料 在半导体中的阱区域被多孔化并且在传感器元件结构的部分被去除和/或变得多孔的情况下。

公开(公告)号：US06506621B1

公开(公告)日：2003-01-14

申请号：US10016026

申请日：2001-12-12

Applicant: Hans Artmann ,  Thorsten Pannek ,  Robert Siegel

Inventor： Hans Artmann ,  Thorsten Pannek ,  Robert Siegel

IPC: H01L2100

CPC classification number: G01J5/06 ,  B81B3/0081 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01J5/10

Abstract: In a method for producing a diaphragm sensor array having a semiconductor material substrate on which a plurality of planar diaphragm regions is arranged as a carrier layer for sensor elements, the planar diaphragm regions are thermally decoupled from one another by crosspieces made of a material having clearly better heat conductive properties compared to the diaphragm regions and the lateral surroundings of the crosspieces. Masking for a subsequent step for producing porous semiconductor material is applied at the locations of the semiconductor material substrate at which the crosspieces for the thermal decoupling are formed, and the semiconductor regions not protected by the masking are rendered porous and the diaphragm regions are produced thereupon. Instead of using porous silicon, a plasma etching process may be performed from the backside of a semiconductor material substrate. In particular, high integration densities of diaphragm sensors may be achieved with both methods. A diaphragm sensor array is produced by one of the methods.

Abstract translation: 在具有半导体材料基板的膜片传感器阵列的制造方法中，多个平面膜片区域被布置为传感器元件的载体层，平面隔膜区域通过由具有清楚的材料制成的横条而彼此热分离 与隔膜区域和横梁的横向周围相比，具有更好的导热性能。 在用于制造多孔半导体材料的后续步骤中的掩模被应用于半导体材料基板的用于形成用于热解耦的接头的位置处，并且未被掩蔽保护的半导体区域变得多孔，并且在其上产生隔膜区域 。 代替使用多孔硅，可以从半导体材料基板的背面进行等离子体蚀刻工艺。 特别地，可以通过两种方法实现膜片传感器的高集成度。 通过这些方法之一产生膜片传感器阵列。