公开(公告)号：KR1020170026957A

公开(公告)日：2017-03-09

申请号：KR1020150123195

申请日：2015-08-31

Applicant: 삼성디스플레이 주식회사

Inventor： 김무겸

IPC: H05B33/14 ,  H05B37/00 ,  G09F9/30 ,  G09F9/302 ,  G09F9/33 ,  F21K99/00 ,  H01L33/00

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/03002 ,  H01L2224/04 ,  H01L2224/80003 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80224 ,  H01L2224/80401 ,  H01L2224/80417 ,  H01L2224/80423 ,  H01L2224/80424 ,  H01L2224/80438 ,  H01L2224/80439 ,  H01L2224/80444 ,  H01L2224/80447 ,  H01L2224/80455 ,  H01L2224/80464 ,  H01L2224/80466 ,  H01L2224/80469 ,  H01L2224/80471 ,  H01L2224/80478 ,  H01L2224/8048 ,  H01L2224/80484 ,  H01L2224/81001 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81401 ,  H01L2224/81417 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81438 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81471 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81484 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2224/95085 ,  H01L2224/951 ,  H01L2224/95136 ,  H01L2224/95144 ,  H01L2224/97 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0106 ,  H01L2924/01003 ,  H01L2924/0102 ,  H01L2224/80 ,  H01L2224/81 ,  H01L2221/68304 ,  H01L21/78 ,  H01L2221/68381

Abstract: 본발명의일 측면에따르면, 복수의개구가형성된마스크를용액에담그고, 상기마스크의각 개구에 LED 칩을안착시킴; 복수의제1 배선이형성된제1 플렉서블기판을상기마스크아래에배치하고, 상기복수의제1 배선을상기개구의위치에대응되도록정렬함; 상기마스크와함께상기제1 플렉서블기판을용액밖으로꺼내고, 상기복수의 LED 칩과상기복수의제1 배선을접합함; 상기복수의 LED 칩위에, 복수의제2 배선이형성된제2 플렉서블기판을정렬하고, 상기복수의 LED 칩과상기복수의제2 배선을접합함;을포함하는표시장치의제조방법을제공한다.

Abstract translation: 制造显示装置的方法包括：将包括开口的掩模浸入溶液中; 将座位发光二极管芯片分别放置在掩模的开口中; 在所述掩模下面布置包括第一布线的第一柔性基板，并且将所述第一布线对准于所述掩模的开口; 从溶液中除去第一柔性基板，其中第一布线对应于掩模的开口与掩模一起，发光二极管芯片位于其开口中; 将发光二极管芯片和第一布线彼此接合; 提供第二柔性基板，其上包括第二布线，并且将所述第二布线对准分别对应于所述发光二极管芯片; 并且将发光二极管芯片和第二布线彼此接合，以形成显示装置。

公开(公告)号：KR1020150006845A

公开(公告)日：2015-01-19

申请号：KR1020147031522

申请日：2013-04-24

Applicant: 본드테크 가부시키가이샤 ,  스가 다다또모

Inventor： 스가다다또모 ,  야마우치아키라

IPC: H01L25/065 ,  H01L21/60 ,  H01L25/07 ,  H01L21/302 ,  H01L21/324

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2201/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: 접합 계면에 수지 등의 바람직하지 않은 잔존물을 남기지 않도록 하여 칩과 웨이퍼 사이 또는 적층된 복수의 칩 사이의 전기적 접속을 확립하여 기계적 강도를 올리는 웨이퍼 상에 칩을 효율적으로 접합하는 기술을 제공하는 것. 금속 영역을 가지는 칩측 접합면을 가지는 복수의 칩을 복수의 접합부를 가지는 기판에 접합하는 방법이, 칩측 접합면의 금속 영역을 표면 활성화 처리하고 또한 친수화 처리하는 단계(S1)와, 기판의 접합부를 표면 활성화 처리하고 또한 친수화 처리하는 단계(S2)와, 표면 활성화 처리되면서 친수화 처리된 복수의 칩을 각각 칩의 금속 영역이 기판의 접합부에 접촉하도록 표면 활성화 처리되면서 친수화 처리된 기판의 대응하는 접합부 상에 장착하는 단계(S3)와, 기판과 기판 상에 장착된 복수의 칩을 포함하는 구조체를 가열하는 단계(S4)를 구비한다.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US20240297143A1

公开(公告)日：2024-09-05

申请号：US18654016

申请日：2024-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHIH-YUAN CHIU ,  SHIH-YEN CHEN ,  CHI-CHUN PENG ,  HONG-KUN CHEN ,  HUI-TING LIN

IPC: H01L23/00 ,  H01L21/683

CPC classification number: H01L24/74 ,  H01L21/6838 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80047 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80908

Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.

公开(公告)号：US12015008B2

公开(公告)日：2024-06-18

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US12009337B2

公开(公告)日：2024-06-11

申请号：US17672285

申请日：2022-02-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chih-Yuan Chiu ,  Shih-Yen Chen ,  Chi-Chun Peng ,  Hong-Kun Chen ,  Hui-Ting Lin

IPC: H01L23/00 ,  H01L21/683

CPC classification number: H01L24/74 ,  H01L21/6838 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80047 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80908

Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.

公开(公告)号：US11973055B2

公开(公告)日：2024-04-30

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

公开(公告)号：US20240079364A1

公开(公告)日：2024-03-07

申请号：US18151856

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Hsu ,  Jian-Wei Hong ,  Kuo-Chiang Ting ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9212 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/0549 ,  H01L2924/05494 ,  H01L2924/07025

Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.

公开(公告)号：US11729973B2

公开(公告)日：2023-08-15

申请号：US17160563

申请日：2021-01-28

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H10B43/27 ,  H01L25/065 ,  H01L23/00 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L24/04 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05095 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US10037968B2

公开(公告)日：2018-07-31

申请号：US15589513

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Xiaomeng Chen ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC: H01L21/68 ,  H01L23/00 ,  H01L21/67

CPC classification number: H01L24/94 ,  H01L21/67092 ,  H01L21/681 ,  H01L24/08 ,  H01L24/74 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00015 ,  H01L2224/80121 ,  H01L2924/00

Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.