公开(公告)号：EP2512036B1

公开(公告)日：2018-06-06

申请号：EP10849705.8

申请日：2010-07-19

Applicant: ZTE Corporation

Inventor： ZHANG, Lu

IPC: H04B1/40 ,  H04M1/02 ,  H05K1/02

CPC classification number: H05K1/02 ,  H05K1/0224 ,  H05K1/0298 ,  H05K3/00 ,  H05K2201/09145 ,  H05K2201/09354 ,  Y10T29/49124

Abstract: The disclosure discloses a wireless terminal with a reduced Specific Absorption Rate (SAR) peak. The wireless terminal comprises a Printed Circuit Board (PCB), wherein a fractal gap is formed at an edge of a metal ground on the PCB to disturb distribution of induced current at the edge of the metal ground. The disclosure also discloses a method for reducing an SAR peak. On the premise of the non-influence on the communication quality of the wireless terminal, the SAR and the production cost can be reduced and the structure space of wireless terminal can be saved by using the wireless terminal and the method.

公开(公告)号：EP3160214A1

公开(公告)日：2017-04-26

申请号：EP16171916.6

申请日：2016-05-30

Applicant: LG Display Co., Ltd.

Inventor： PYUN, UnSeung

IPC: H05K1/02

CPC classification number: H05K1/0259 ,  G02F1/13 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/092 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/147 ,  H05K2201/0919 ,  H05K2201/09354 ,  H05K2201/09618 ,  H05K2201/10128 ,  H05K2201/10409

Abstract: A PCB (100) underneath the display panel (320) includes a plurality of insulation layers (111, 113, 115, 117, 119) and one or more metal layers disposed between two adjacent insulation layers out of the plurality of insulation layers (111, 113, 115, 117, 119). A lower structure (330) is disposed between the display panel (320) and the PCB (100). At least a portion of a metal layer among the one or more metal layers that is most adjacent to the lower structure (330) is exposed, and the lower structure (330) is electrically connected to the exposed portion of the metal layer (112). Such exposed portion of the metal layer (112) is electrically connected to the lower structure (330), so that the area where the PCB (100) is referenced to the ground potential is increased. As a result, residual voltage, residual current in the PCB (100) and noise caused by electromagnetic fields generated thereby can be reduced.

Abstract translation: 位于显示面板（320）下方的PCB（100）包括多个绝缘层（111,113,115,117,119）以及设置在多个绝缘层中的两个相邻绝缘层之间的一个或多个金属层（111 ，113,115,117,119）。 下部结构（330）设置在显示面板（320）和PCB（100）之间。 在与下部结构（330）最邻近的一个或多个金属层中的至少一部分金属层被暴露，并且下部结构（330）电连接到金属层（112）的暴露部分， 。 金属层（112）的这种暴露部分电连接到下部结构（330），使得PCB（100）参考地电位的区域增加。 结果，可以降低PCB（100）中的残余电压，剩余电流和由此产生的电磁场所引起的噪声。

公开(公告)号：EP2743980A2

公开(公告)日：2014-06-18

申请号：EP13196705.1

申请日：2013-12-11

Applicant: Wintek Corporation

Inventor： Chu, Kuan-Yu ,  Huang, Chen-Fu ,  Liu, Chiu-Mei ,  Chen, Ming-Wu ,  Hwang, Chin-Pei ,  Huang, Chun-Cheng ,  Wang, Yu-Ching ,  Li, Chung-Hsien ,  Chen, Kuo-Hsing ,  Chen, Yu-Ting ,  Su, Chen-Hao

IPC: H01L23/498

CPC classification number: H02H9/02 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04107 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0259 ,  H05K1/117 ,  H05K2201/0108 ,  H05K2201/0326 ,  H05K2201/0338 ,  H05K2201/09354 ,  H05K2201/09727 ,  H01L2924/00

Abstract: A lead structure disposed on a substrate is provided. The substrate includes a display area disposed with a device and a peripheral area disposed with a lead structure including first pads, a second pad, first traces and a second trace. The first traces are connected to the device. Each first trace has a first linear portion and a first bonding portion connected together. Each first trace is electrically connected to one of the first pads through the first bonding portion. The second trace has a second linear portion and a second bonding portion connected together. The second trace is electrically connected to the second pad through the second bonding portion. A width of the first linear portion is smaller than a width of the first bonding portion, and a width of the second linear portion is smaller than a width of the second bonding portion.

Abstract translation: 设置在基板上的引线结构。 衬底包括布置有器件的显示区域和设置有包括第一焊盘，第二焊盘，第一迹线和第二迹线的引线结构的周边区域。 第一条迹线连接到设备。 每个第一迹线具有连接在一起的第一直线部分和第一接合部分。 每个第一迹线通过第一结合部分电连接到第一焊盘之一。 第二迹线具有连接在一起的第二直线部分和第二接合部分。 第二迹线通过第二接合部电连接到第二焊盘。 第一直线部分的宽度小于第一接合部分的宽度，并且第二直线部分的宽度小于第二接合部分的宽度。

公开(公告)号：EP1776827B1

公开(公告)日：2013-11-06

申请号：EP05724119.2

申请日：2005-03-02

Applicant: Sony Ericsson Mobile Communications AB

Inventor： HAYES, Gerard James ,  VANCE, Scott LaDell

IPC: H04B1/38 ,  H05K1/02

CPC classification number: H05K9/0039 ,  H04B1/3838 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10446

公开(公告)号：EP2354814A1

公开(公告)日：2011-08-10

申请号：EP09830443.9

申请日：2009-12-03

Applicant: Fujikura, Ltd.

Inventor： OSAKI, Takuya ,  KONDO, Masahiro ,  SAKIYAMA, Koji

IPC: G01V3/08 ,  G01B7/00 ,  G01B7/28 ,  H01H36/00 ,  H01R12/04 ,  H01R12/32 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H03K17/955 ,  H01R12/69 ,  H01R13/6683 ,  H03K2017/9602 ,  H03K2217/94094 ,  H03K2217/960705 ,  H05K1/117 ,  H05K1/118 ,  H05K2201/09318 ,  H05K2201/09354 ,  H05K2201/09781 ,  H05K2201/10189

Abstract: Disclosed is an electrical capacitance sensor comprising: a board 10 having a one main surface and an other main surface; a sensor electrode 26 formed on the one main surface of the board 10 and detecting an electrical capacitance between the sensor electrode 26 and an object; a first guard electrode 25 formed on the one main surface of the board 10 and in a vicinity of the sensor electrode 26; and a second guard electrode 27 formed on the other main surface of the board 10, wherein a first terminal connecting portion 21 for the first guard electrode 25 and a second terminal connecting portion 23 for the second guard electrode 27 are provided at positions opposing each other.

Abstract translation: 公开了一种电容传感器，包括：板10，其具有一个主表面和另一个主表面; 形成在板10的一个主表面上并检测传感器电极26与物体之间的电容的传感器电极26; 形成在板10的一个主表面上并在传感器电极26附近的第一保护电极25; 以及形成在板10的另一个主表面上的第二保护电极27，其中第一保护电极25的第一端子连接部分21和第二保护电极27的第二端子连接部分23设置在彼此相对的位置 。

公开(公告)号：EP1901110B1

公开(公告)日：2010-10-27

申请号：EP07016885.1

申请日：2007-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang, Hyun-min

IPC: G02F1/13 ,  H05K1/14 ,  G02F1/13357

CPC classification number: G02F1/13452 ,  G02F1/133608 ,  H05K1/0218 ,  H05K1/0224 ,  H05K1/118 ,  H05K1/148 ,  H05K3/361 ,  H05K2201/09354 ,  H05K2201/0949 ,  H05K2201/09618 ,  H05K2201/09681 ,  H05K2201/10136

公开(公告)号：EP2057868A1

公开(公告)日：2009-05-13

申请号：EP07811240.6

申请日：2007-08-10

Applicant: Tyco Electronics Corporation

Inventor： BARTHOLOMEW, Victor L.

IPC: H05K1/02

CPC classification number: H05K1/0219 ,  H05K1/0201 ,  H05K1/0293 ,  H05K1/117 ,  H05K3/3405 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/062 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2201/0969 ,  H05K2201/10356 ,  H05K2203/173 ,  Y10S439/943 ,  Y10T29/49155

Abstract: A transition circuit board (100) for transitioning a cable to a connector is provided. A circuit board has an outer surface (104) with a circuit trace (106), ground plane (120) and ground link (118) provided thereon. A cable pad (114) and a contact pad (116) are provided at opposite ends of the circuit trace. The ground link is electrically common with the ground plane and is located adjacent to, and separated by a space from, the circuit trace. An insulating coating (168) is provided over at least part of the circuit trace, the ground plane and the outer surface of the circuit board. The insulating coating has a mask aperture there-through exposing an uncoated portion of the circuit trace and the ground link. A conductive jumper material is provided on the uncoated portion of the circuit trace and the ground link to electrically join the circuit trace with the ground plane.

公开(公告)号：EP1418798B1

公开(公告)日：2007-06-13

申请号：EP03024969.2

申请日：2003-10-29

Applicant: KONICA MINOLTA HOLDINGS, INC.

Inventor： Kishimoto, Tadao ,  Igarashi, Yutaka ,  Hirayama, Hironobu

IPC: H05K7/04

CPC classification number: H05K1/0234 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/325 ,  H05K3/429 ,  H05K7/142 ,  H05K9/0039 ,  H05K2201/09354 ,  H05K2201/09618 ,  H05K2201/10022 ,  H05K2201/10409 ,  H05K2201/10446 ,  Y10T29/49155

公开(公告)号：EP1418798A2

公开(公告)日：2004-05-12

申请号：EP03024969.2

申请日：2003-10-29

Applicant: KONICA MINOLTA HOLDINGS, INC.

Inventor： Kishimoto, Tadao ,  Igarashi, Yutaka ,  Hirayama, Hironobu

IPC: H05K7/04

CPC classification number: H05K1/0234 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/325 ,  H05K3/429 ,  H05K7/142 ,  H05K9/0039 ,  H05K2201/09354 ,  H05K2201/09618 ,  H05K2201/10022 ,  H05K2201/10409 ,  H05K2201/10446 ,  Y10T29/49155

Abstract: There is described a multi-layer printed circuit board and a method of installing it. The circuit board includes a first signal layer formed on its obverse surface; a ground layer arranged at a position next to the first signal layer; an electronic power source layer arranged at a position next to the ground layer; and a second signal layer formed on its reverse surface. The first and second patterns are formed around peripheral areas of the first and second signal layers, respectively. The first ground pattern and the second ground pattern are electrically coupled to each other by plural through holes, and the multi-layer printed circuit board is installed on an electro-conductive housing in such a manner that a substantially whole area of the second ground pattern electrically contacts a mounting area of the electro-conductive housing, the mounting area being an electro-conductive area continuously coupled to the electro-conductive housing.

Abstract translation: 描述了一种多层印刷电路板及其安装方法。 电路板包括在其正面上形成的第一信号层; 布置在与所述第一信号层相邻的位置处的接地层; 布置在接地层旁边的位置处的电子电源层; 以及在其反面上形成的第二信号层。 第一和第二图案分别形成在第一和第二信号层的周边区域周围。 第一接地图案​​和第二接地图案通过多个通孔彼此电耦合，并且多层印刷电路板以这样的方式安装在导电外壳上，使得第二接地图案的大致整个区域 电接触导电壳体的安装区域，安装区域是连续地耦合到导电壳体的导电区域。

公开(公告)号：EP0278869A3

公开(公告)日：1990-11-07

申请号：EP88400301.3

申请日：1988-02-09

Applicant: AUGAT INC.

Inventor： Kendall, Jerry A. ,  Morse, Gary L. ,  Webb, David M.

IPC: H01R23/70

CPC classification number: H05K1/117 ,  H01R12/716 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09781 ,  H05K2203/167 ,  Y10S439/951

Abstract: A circuit pattern on the surface of a printed circuit board used as a guide and connection circuit for closely spaced contacts of a connector to be connected to the circuit board. The contacts of the connector are closely spaced and possibly would not contact the connection pads (80) or might be located between connection pads (80) because of the close spacing of the contacts. The guides (70) formed from circuit patterns accurately guide the connector to the connector pads (80) on the circuit board and place each contact over its respective circuit connection pad.