公开(公告)号：JP2001155499A

公开(公告)日：2001-06-08

申请号：JP2000317923

申请日：2000-10-18

Applicant: ST MICROELECTRONICS INC ,  FUJITSU LTD

Inventor： MCCLURE DAVID CHARLES ,  COKER THOMAS ALLYN

IPC: G06F11/22 ,  G01R31/317 ,  G11C29/14 ,  G11C29/46 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and a method permitting a special operation mode, and a circuit and a method decreasing possibility in which erroneous entry is performed for a special operation mode by unexpected acci dental operation, in an integrated circuit having a special operation mode such as a special test mode and the like as well as a normal operation mode. SOLUTION: In order to permit a special operation mode such as a test mode or the like, it can be incorporated in a memory device provided with a circuit requiring over-voltage excursion (deviation) of plural pieces of special terminals. The circuit has plural flip-flop, each of them is clock-operated by each over-voltage excursion, and the last one in the series generates an internal test enable-signal. The flip-flop are connected in series in a mode in which an enable-signal passes through in a ripple state through the flip-flop with each over-voltage condition. When plural test modes can be selected, plural series are provided.

公开(公告)号：JP2001148169A

公开(公告)日：2001-05-29

申请号：JP2000298957

申请日：2000-09-29

Applicant: ST MICROELECTRONICS INC

Inventor： OZDEMIR HAKAN ,  REZZI FRANCESCO

IPC: G11B20/14 ,  G11B20/16 ,  H03M13/41 ,  H04L7/04 ,  H04L7/08

Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and a method for restoring synchronous information from a signal. SOLUTION: This synchronizing circuit has an input terminal, an output terminal, and a restoring circuit coupled to the input terminal and the output terminal. The input terminal receives an input signal having a synchronizing mark. the restoring circuit restores a synchronizing mark from the input signal and can operate, so that a synchronizing signal is generated on the output terminal responding to the restored synchronizing mark.

公开(公告)号：JP2001038906A

公开(公告)日：2001-02-13

申请号：JP2000226252

申请日：2000-07-27

Applicant: ST MICROELECTRONICS INC

Inventor： HOPKINS THOMAS L

IPC: B41J2/05 ,  B41J2/14

Abstract: PROBLEM TO BE SOLVED: To provide a multi-output driver circuit for a thermal ink jet printing head simplified in a structure so as to dispense with one amplifier circuit per each power output transistor. SOLUTION: A monolithically integrated multi-output power driver circuit 66 is formed as a semiconductor integrated circuit to be connected to the respective heating elements in a printing head 50 and has the power MOS transistor connected to the respective heating elements. A reference circuit is operationally connected to the respective gates of the power MOS transistor and has a reference transistor equipped with gates and a reference amplifier receiving a reference voltage and current supply source as input. The output of the amplifier is operationally connected to the gates of the power output transistor and the gates of the reference transistor. The reference amplifier adjusts the reference transistor directly and adjusts the power MOS transistor by matching.

公开(公告)号：JP2000353396A

公开(公告)日：2000-12-19

申请号：JP2000128910

申请日：2000-04-28

Applicant: ST MICROELECTRONICS INC

Inventor： BRADY JAMES

IPC: G01R31/28 ,  G06F12/16 ,  G11C11/401 ,  G11C11/413 ,  G11C17/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/52 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To decide whether a memory array and a related circuit are operated in an appropriate condition or not by comparing a read-out data signal read out from the prescribed memory cell and stored in a second storing circuit with a stored write-in data signal. SOLUTION: Write-in data signals stored in memory cells of the prescribed numbers are read out from a memory cell, and read-out data signals of corresponding numbers are generated. A read-out data signal is supplied to a try-state inverter circuit 94 through a pair of true and complemental column I/O line and a local bus 92, and transmitted to a corresponding data comparison block circuit 96. After the data comparison block circuit 96 latches corresponding read-out data signal, the circuit compares a write-in data signal previously latched with a read-out data signal latched lately. Thus, it is decided whether the circuit is operated in an appropriate condition or not.

公开(公告)号：JP2000251209A

公开(公告)日：2000-09-14

申请号：JP2000048610

申请日：2000-02-25

Applicant: ST MICROELECTRONICS INC

Inventor： PAKRISWAMY ELANGO

IPC: G11B5/012 ,  G11B5/035 ,  G11B5/09 ,  G11B19/04 ,  H03K17/695

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit and the method which speedily drive the H-bridge circuit of a disk drive. SOLUTION: An H-bridge circuit 100 is provided with NMOS transistors(TR) as both upper and lower couples of TRs. An induction head is coupled between the terminals of the TRs. When a logical signal has been received, one of the upper TRs 125 and 165 is driven. The selected upper TRs 125 and 165 to be driven respond to the logical signal. The corresponding lower TRs 145 and 185 are also driven to make a current flow in a 1st direction through the induction head. The driving circuit for the lower TRs 145 and 185 has a programmable circuit, which is constituted by capacitively coupling the output terminal of the driving circuit with a pull-up voltage so as to maximize the quantity of the current forcibly made to flow through the induction head for optimum data transfer.

公开(公告)号：JP2000196026A

公开(公告)日：2000-07-14

申请号：JP36093299

申请日：1999-12-20

Applicant: ST MICROELECTRONICS INC

Inventor： ARNAUD EVE LUPERT ,  DANIEL A THOMAS

IPC: H01L27/04 ,  A61B5/117 ,  G01B7/28 ,  G01B7/34 ,  G06K9/00 ,  G06T1/00 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To enhance a sensor in electrostatic discharge protection by a method wherein a composite insulating layer is formed between conductive plates and above them to isolate the conductive plates, and the conductive plates are protected against damage. SOLUTION: Pixels are formed on a silicon substrate 13. A dielectric layer 30 is formed on the conductive plates 10 and 12 and the substrate 13 through a plasma enhancement vapor growth method so as to be thick enough to electrically isolate the conductive plates 10 and 12 and the substrate 13. The dielectric layer 30 is a composite layer composed of a first dielectric layer 30' and a second dielectric layer 32 which are each formed of suitable dielectric material that has a required dielectric constant. A conductive layer 32 is provided on a part of the dielectric layer 30. The thickness of the dielectric layer 30 is properly determined depending on the resistivity level of dielectric material to a conductive material in a layer 16 so as to ensure the dielectric layer 30 of an electric charge carrying capacity and a damage protection properties.

公开(公告)号：JP2000174017A

公开(公告)日：2000-06-23

申请号：JP21682199

申请日：1999-07-30

Applicant: ST MICROELECTRONICS INC

Inventor： BRADY JAMES ,  LAURENT DUANE GILES

IPC: H01L21/3205 ,  H01L23/52 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To reduce the propagation delay time of an electric signal transmitted along a conductor in a circuit by extending a second substantially parallel electrically coupled conductor near and along a first electric signal carrying conductor extending from a first section of the circuit to a second section. SOLUTION: A conductor 120 extending from a first circuit 112 located in a first section 114 of an integrated circuit to a second circuit 116 located in a second section 118 is pref. 1000 μm long or more, the conductor 120 has a first conductor 120a and a second and third conductors 120b, 120c, each extending parallel to and along the first conductor 120a. The second conductor 120b is made of a conductive metal or material, pref. a low resistance material contg. Cu, W, Al, polysilicon or other substance, etc. This increases the velocity of an-electric signal propagating along the conductor 120.

公开(公告)号：JP2000156696A

公开(公告)日：2000-06-06

申请号：JP29046699

申请日：1999-10-13

Applicant: ST MICROELECTRONICS INC

Inventor： FUNG ANTHONY ,  PETER GROSS ,  JIM C TSU ,  DANNY K UI ,  HARRY S FOSTOV

IPC: H04L12/40 ,  H04L12/56 ,  H04L12/64

Abstract: PROBLEM TO BE SOLVED: To provide a fast serial bus interface that is based on a 1394-standard by using a queue, etc., having a constitution where every message control block accepts a memory control block including the organized data. SOLUTION: This interface has a queue which accepts a memory control block and this queue has the organized data, a conversion engine which reads the memory control block and converts it into a data packet and an output port which makes the data packet pass through a transmission bay to place the data packet on a bus. When a transaction interface 210 receives a write request to a data quadrate, for example, the interface 210 executes a sequenced set of actions concerned in scheduling such tasks as a command ORB execution task 245 and a fetch management task 215. Each of these tasks has at least a relevant queue.

公开(公告)号：JP2000151713A

公开(公告)日：2000-05-30

申请号：JP27804499

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER

IPC: G06F13/00 ,  H04L12/56 ,  H04L13/08 ,  H04L29/06 ,  H04L12/44

Abstract: PROBLEM TO BE SOLVED: To provide an improved method and a system which perform routing of data adjusted to a frame based on a network. SOLUTION: A host processor 44 starts an address lookup algorithm for analyzing burst of transferred data and feeding a frame to a desired destination. A common system memory 46 receives data including an address field selected in advance. A network device has plural ports and each port has a FIFO reception memory for receiving at least a first part of the frame. This first part has data equipped with the address field selected beforehand. A DMA unit transfers burst of the data from the FIFO reception memory to the common system memory 46. A communication processor selects an amount of data to be transferred from the FIFO reception memory on the basis of the desired address field to be analyzed by the host processor.

公开(公告)号：JP2000149563A

公开(公告)日：2000-05-30

申请号：JP31105199

申请日：1999-11-01

Applicant: ST MICROELECTRONICS INC

Inventor： BRADY JAMES

IPC: G11C11/409 ,  G11C7/12 ,  G11C11/4094

Abstract: PROBLEM TO BE SOLVED: To provide a device and a method for maintaining, to the allowable range, a sub threshold leak current related to a memory cell of a dynamic memory device buried within an integrated circuit chip. SOLUTION: In view of maintaining a voltage on the bit line higher than the low reference voltage source, a circuit is provided to clamp the voltage appearing on the bit lines 3, 4 of a dynamic random access memory(DRAM) device. This circuit also includes a pull-up device 20A connected to the bit line of the DRAM device. The pull-up device 20A becomes active only when the pull-down device connected to the bit line pulls some of the bit lines toward the low reference voltage level.