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    FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF
    102.
    发明公开
    FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF 审中-公开
    对于集成掩模可编程逻辑单元灵活的布局及其制造方法

    公开(公告)号：EP2996248A3

    公开(公告)日：2016-06-08

    申请号：EP15185553.3

    申请日：2007-12-29

    Applicant: STMicroelectronics Design and Application S.R.O.

    Inventor： VACULA, Patrik ,  VACULA, Milos ,  LZICAR, Milan

    IPC: H03K19/177 ,  H03K19/173

    CPC classification number: H03K19/17736 ,  H03K19/1735 ,  H03K19/17796

    Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

    FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF
    103.
    发明公开
    FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF 审中-公开
    柔性布置FÜRINTEGRIERTE MASKENPROGRAMMIERBARE LOGIKEINHEITEN UND HERSTELLUNGSVERFAHRENDAFÜR

    公开(公告)号：EP2996248A2

    公开(公告)日：2016-03-16

    申请号：EP15185553.3

    申请日：2007-12-29

    Applicant: STMicroelectronics Design and Application S.R.O.

    Inventor： VACULA, Patrik ,  VACULA, Milos ,  LZICAR, Milan

    IPC: H03K19/177 ,  H03K19/173

    CPC classification number: H03K19/17736 ,  H03K19/1735 ,  H03K19/17796

    Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

    Abstract translation: 集成掩模可编程装置，具有多个金属层，包括形成在顶部和底部金属层之间的顶部金属层，底部金属层和第一中间金属层，以及布置在底部和底部金属层之间的多个通孔层 中间金属水平和第一中间和顶部金属水平之间并且将每个金属水平连接到相邻的金属水平。 多个金属层形成第一，第二和至少第三末端，顶部和底部金属层具有至少两个金属区域，并且第一中间金属层具有至少三个金属区域。 第一端子连接到第三端子，或者通过修改单个金属或通孔电平将第二端子连接到第三端子。

    Capacitive load driving amplifier
    104.
    发明公开
    Capacitive load driving amplifier 有权
    Antriebsverstärkerfürkapazitive Lasten

    公开(公告)号：EP2341616A1

    公开(公告)日：2011-07-06

    申请号：EP09180680.2

    申请日：2009-12-23

    Applicant: STMicroelectronics Design and Application S.R.O.

    Inventor： Murin, Peter ,  Folk, Tomas ,  Panus, Pavel

    IPC: H03F3/45

    CPC classification number: H03F3/45183 ,  H03F3/45475

    Abstract: The invention relates to an electronic amplifier (100) for driving a capacitive load (C), which comprises a first and a second differential input terminals (IN1, IN2) to receive an input signal (Vin), and first (OUT1) and second (OUT2) differential output terminals to provide a differential output signal (Vout). The amplifier further comprises:
    - a first (101) operational device having a first (S-) and a second (S+) differential inputs connected to the first and second input terminals (IN1, IN2), respectively, and an output connected to the first output terminal (OUT1), and
    - a second (102) operational device having a further first (T+) and a further second (T-) differential inputs connected to the first and second input terminals (IN1, IN2), respectively, and a further output connected to the second output terminal (OUT2). The first (101) and second (102) operational devices are operatively configured so that both the first (OUT1) and the second (OUT2) output terminals are sunk to a same reference potential (GND) during periods in which a module of differential output signal (Vout) amplitude decrease.

    Abstract translation: 本发明涉及一种用于驱动电容性负载（C）的电子放大器（100），其包括用于接收输入信号（Vin）的第一和第二差分输入端（IN1，IN2）和第一（OUT1）和第二 （OUT2）差分输出端子提供差分输出信号（Vout）。 放大器还包括： - 第一（101）操作装置，具有分别连接到第一和第二输入端子（IN1，IN2）的第一（S）和第二（S +）差分输入端，以及连接到 第一输出端子（OUT1）和 - 第二（102）操作装置，其具有分别连接到第一和第二输入端子（IN1，IN2）的另外的第一（T +）和另外的第二（T）差分输入，以及 连接到第二输出端（OUT2）的另一输出。 第一（101）和第二（102）操作装置可操作地构造成使得在差分输出模块的时段期间，第一（OUT1）和第二（OUT2）输出端都被吸入相同的参考电位（GND） 信号（Vout）振幅减小。

    Control device for a constant current flyback converter
    105.
    发明公开
    Control device for a constant current flyback converter 审中-公开
    Steuereinrichtungfüreinen Konstantstromsperrwandler

    公开(公告)号：EP2254227A1

    公开(公告)日：2010-11-24

    申请号：EP10162502.8

    申请日：2010-05-11

    Applicant: STMicroelectronics Design and Application S.R.O.

    Inventor： Koutensky, Pavel

    IPC: H02M3/335 ,  H05B33/08

    CPC classification number: H05B33/0815 ,  H02M3/33523

    Abstract: A control device (100) for regulating the constant output current of a flyback converter is disclosed. The flyback converter has an input voltage (Vinr) and outputs a direct output voltage (Vout) with a constant output current (Iout) to supply the load (6); the flyback converter comprises a transformer (10) with a primary winding (L1) coupled with the direct input voltage and a secondary winding (L2) coupled with the direct output voltage and a switch (M) coupled to the primary winding to regulate the current (Ip) flowing through the primary winding and regulate the output direct voltage. The control device (100) is adapted to control the switch determining the on time period (Ton) and the off time period (Toff) of the switch and comprises first means (5) adapted to multiply a first signal (14) representative of the current flowing through the primary winding and a second signal (V3) representative of the direct input voltage and outputting a signal (V2) representative of said multiplication, second means (4) adapted to compare the output signal (V2) of the first means and a third signal (V1) representative of the direct output voltage. The control device is adapted to determine, on the base of the output signal (E) of said second means, said on time period and said off time period of the switch so that the output signal of the first means is made equal to the signal representative of the direct output signal to have the constant output current of the flyback converter.

    Abstract translation: 公开了一种用于调节反激式转换器的恒定输出电流的控制装置（100）。 反激式转换器具有输入电压（Vinr）并输出具有恒定输出电流（Iout）的直接输出电压（Vout）以提供负载（6）; 反激转换器包括具有与直接输入电压耦合的初级绕组（L1）和与直接输出电压耦合的次级绕组（L2）的变压器（10）和耦合到初级绕组的开关（M），以调节电流 （Ip）流过初级绕组并调节输出直流电压。 控制装置（100）适于控制开关确定开关的接通时间段（Ton）和关断时间段（Toff），并且包括第一装置（5），适于将代表 流过初级绕组的电流和表示直接输入电压的第二信号（V3），并输出表示所述乘法的信号（V2），第二装置（4）适于将第一装置的输出信号（V2）和 代表直接输出电压的第三信号（V1）。 控制装置适于基于所述第二装置的输出信号（E）确定所述开关的所述接通时间段和所述关闭时间段，使得所述第一装置的输出信号等于所述信号 代表直接输出信号具有恒定的反激式转换器的输出电流。

    A METHOD OF CONTROLLING ELECTRIC MOTORS, CORRESPONDING DEVICE AND MOTOR
    108.
    发明公开
    A METHOD OF CONTROLLING ELECTRIC MOTORS, CORRESPONDING DEVICE AND MOTOR 审中-公开
    一种控制电动机的方法，相应的装置和电动机

    公开(公告)号：EP3264586A1

    公开(公告)日：2018-01-03

    申请号：EP16425066.4

    申请日：2016-06-28

    Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

    Inventor： Ryba, Jiri ,  Forte, Gianluigi ,  Spampinato, Andrea

    IPC: H02P6/18

    CPC classification number: H02P6/183 ,  H02P6/18

    Abstract: An electric motor including a plurality of windings (A, B, C), may be driven by: _
    - sensing (12) currents ( i a *, i b *, i c *) in the motor windings (A, B, C),
    - generating (14, 16) a motor rotation angle signal (θ) from the currents sensed ( i a *, i b *, i c *),
    - generating (10) motor control voltages ( V a , V b , V c ) as a function of the motor rotation angle signal (θ),
    - driving (18) the motor windings with motor drive voltages ( V a *, V b * , V c ) obtained by injecting into the motor control voltages ( V a , V b , V c ) injection pulses ( V ainj , V binj , V cinj ), wherein the currents sensed ( i a *, i b * , i c *) include torque components ( i a0 , i b0 , i c0 ), and injection components ( i ainj , i binj , i cinj ), and
    - generating (14, 16) the motor rotation angle signal (θ) as a function of the injection components ( i ainj , i binj , i cinj ) of the currents sensed ( v a *, i b * , i c *).

    Abstract translation: 包括多个绕组（A，B，C）的电动机可以通过以下方式来驱动： - 感测电动机绕组（A，B，C）中的电流（ia *，ib *，ic *）， - 从所感测的电流（ia *，ib *，ic *）生成（14,16）电机旋转角度信号（θ）， - 生成（10）电机控制电压（Va，Vb，Vc） 电动机旋转角度信号（θ）， - 通过将电动机驱动电压（Va *，Vb *，Vc）注入到电动机控制电压（Va，Vb，Vc）中获得喷射脉冲（Vainj，Vbinj ，Vcinj），其中感测到的电流（ia *，ib *，ic *）包括转矩分量（ia0，ib0，ic0）和注入分量（iainj，ibinj，icinj），以及 - 生成（14,16）电动机 旋转角度信号（θ）作为感测电流（va *，ib *，ic *）的注入分量（iainj，ibinj，icinj）的函数。

    METHOD OF MANAGING MEMORIES, CORRESPONDING DEVICE AND APPARATUS
    109.
    发明公开
    METHOD OF MANAGING MEMORIES, CORRESPONDING DEVICE AND APPARATUS 审中-公开
    的管理方法辐条，相关设备和设置

    公开(公告)号：EP3139275A1

    公开(公告)日：2017-03-08

    申请号：EP16162366.5

    申请日：2016-03-24

    Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

    Inventor： MANGANO, Daniele ,  CARRANO, Michele Alessandro ,  DISTEFANO, Gaetano ,  FRIED, Antonin

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1044 ,  G11C29/52

    Abstract: In an embodiment, a method of managing memories (10) includes:
    - providing a first (11) memory module and a second memory module (12) each including a first (R1, R2) and a second (R4, R3) partition,
    - writing first data (DATA1) in the first partition (R1) of the first memory module (11) and second data (DATA2) in the first partition (R2) of the second memory module (12), and
    - selectively operating the first (11) and second (12) memory modules in a first operating mode or a second operating mode, where:
    - in the first operating mode, parity bits (PAR1) for the first data (DATA1) are written in the second partition (R3) of the second memory module (12) and parity bits (PAR2) for the second data (DATA2) are written in the second partition (R4) of the first memory module (11),
    - in the second operating mode, further data (ED1, ED2) are written in the place of parity bits (PAR1, PAR2) in the second partition (R4, R3) of one or both the first memory module (11) and the second memory module (12).

    Abstract translation: 在实施例中，管理存储器（10）的方法包括： - 提供第一（11）存储器模块和第二存储器模块（12）每个都包括第一（R1，R2）和第二（R4，R3）的分区， - 在所述第一分区中的第一存储器模块的（R 1）（11）和在所述第一分区中的第二存储器模块的（R 2）（12）的第二数据（DATA2）写入第一数据（DATA1），以及 - 选择性地操作所述第一 （11）和第二在第一操作模式或第二操作模式，其中，（12）的存储器模块： - 在第一操作模式中，对于第一数据的奇偶校验位（PAR1）（DATA1）被写入到第二分区（R3 ）所述第二存储器模块（12）和用于所述第二数据的奇偶校验位（PAR2）（DATA2）的被写入到第二分区中的第一存储器模块的（R4）（11） - （在第二操作模式中，进一步的数据 ED1，ED2）被写入在一个或两个所述第一存储器模块（11的在第二分区中的奇偶校验位（PAR1，PAR2）（R4，R3））和所述第二存储器模块的地方 （12）。

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