公开(公告)号：JPH08166841A

公开(公告)日：1996-06-25

申请号：JP15256495

申请日：1995-05-25

Applicant: TANDEM COMPUTERS INC

Inventor： HAWAADO JIEI BOOCHIYUU ,  MARII EICHI HENSUKU

IPC: G06F3/00 ,  G06F13/40

Abstract: PURPOSE: To easily realize reliable bus routing structure and to improve its flexibility. CONSTITUTION: Plural parallel bus segments 22a-22h are incorporated to a substrate where a device connector is provided in a module-type bus routing system. The respective end parts of the respective bus segments are connected to the connectors 24a and 24b which are attached to the substrate. Mutual connection between the different bus segments of the substrate is executed by a flexible cable adding a bus conductor which is provided with controlled length and an electric characteristic. A plural personal cards provides various kinds of inter-bus-segment connection states so as to permit the different bus segment to be ended and to be jumper-connected to another segment of the substrate. The different personal card is selected so that the plural bus segments in a certain specified substrate are constituted as a serially connected and single bus or two, four or eight parallel bus.

公开(公告)号：JPH0863532A

公开(公告)日：1996-03-08

申请号：JP18780295

申请日：1995-06-30

Applicant: TANDEM COMPUTERS INC

Inventor： DABURIYU DEIRU HOPUKINSU

IPC: G07F19/00 ,  G06Q20/04 ,  G06Q20/10 ,  G06Q20/12 ,  G06Q20/20 ,  G06Q20/32 ,  G06Q20/34 ,  G06Q20/36 ,  G06Q20/38 ,  G06Q20/40 ,  G06Q20/42 ,  G07F7/00 ,  G07F7/08 ,  G07F7/10 ,  G06F19/00

Abstract: PURPOSE: To attain the remote financial transaction secured highly. CONSTITUTION: This remote financial transaction system uses a payment module accessible to a memory and able to be communicated with an off-site processing system via, e.g. an interactive network. The payment module accesses payment account information stored in the memory and personal identification information corresponding to it. The user selects a desired remote financial transaction and a payment account to be accessed (440). The personal identification information and the required payment account information are read from the memory and ciphered (450) and sent to a financial organ having the account finally via the interactive network (460). The financial organ decides whether the selected remote financial transaction is accepted or rejected and sends a message denoting the acceptance or rejection to the user via the interactive network.

公开(公告)号：JPH07175537A

公开(公告)日：1995-07-14

申请号：JP14900394

申请日：1994-06-30

Applicant: TANDEM COMPUTERS INC

Inventor： MAAKU EI TEIRAA ,  SAMUSON KEI TOI

IPC: G06F1/28 ,  G05F1/56 ,  G06F12/16 ,  G11C11/413 ,  H02J7/00 ,  H02J9/06

Abstract: PURPOSE: To generate a regulated low D.C. voltage from a pair of redundant batteries by providing a control circuit means with an unregulated voltage for generating a control signal and a sensing means connected to the control circuit means. CONSTITUTION: A regulator system 10 is provided with a variable impedance connected to the positive terminals of the two batteries VB1 and VB2 in order to supply the regulated voltage Vr. The variable impedance 12 keeps the balance of current which is drawn from the batteries VB1 and VB2 and is functioned to lower the D.C. voltage supplied by the batteries to be the lower voltage Vr . When change is executed from the required adjusted voltage Vr , an error signal Ve is generated by the control circuit. The regulator system 10 is provided with respectively related battery sensing circuits 16a and 16b as against the batteries VB1 and VB2 and then battery sensing circuits 16 are operated to track the terminal voltages of the respective batteries.

公开(公告)号：JPH07168732A

公开(公告)日：1995-07-04

申请号：JP14450394

申请日：1994-06-27

Applicant: TANDEM COMPUTERS INC

Inventor： JIEFURII EI SUPURAUSU ,  UORUTAA II GIBUSON

IPC: G06F11/22 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G06F13/00 ,  G06F13/36

Abstract: PURPOSE: To provide a digital system provided with many digital sub systems connected with each other by a shared bus structure mutually exclusively accessible so as to communicate data among the digital sub systems. CONSTITUTION: The system 10 is constituted so as to be tested by a pseudo random scanning test method. The respective sub systems 12a-12n are provided with a counter for supplying enable signals to the bus access or driver circuit constitution of the corresponding sub systems during a scanning test period. A scanning test operation is preceded by pre-loading the respective counters in a prescribed state and only one digital sub system drives a shared data bus 14 first and through the test period. Respective scanning sequences clock the counter once, the new sub system can drive the bus 14 in the next sequence and the bus access circuit constitution of the respective sub systems and the bus itself are tested.

公开(公告)号：JPH07154451A

公开(公告)日：1995-06-16

申请号：JP15344594

申请日：1994-07-05

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON SHII FURIIMAN ,  CHIEN GAN KON

IPC: G06F13/00 ,  H04L1/00 ,  H04L29/06 ,  H04L29/14 ,  G06F15/16

Abstract: PURPOSE: To make it possible to reconstitute a system by checking whether a data field generated in specific communication is to be allowed by a communication protocol or inhibited. CONSTITUTION: Respective M and N fields generated from a bus are latched by M and N latches 32, 34 at proper time and respectively sent to a row MUX 35 and a column MUX 36 and unique row and column corresponding to respective fields are selected. A selected output is sent to one input of an output AND gate 38 and a timing window signal (optional) is sent to the other input to generate a clocked error signal. Thus an error check signal for instructing whether a pair of 1st and 2nd data fields are to be allowed by a communication protocol or not is selected, and when the prescribed pair is not allowed by the communication protocol, the selected error check signal stops the specific communication operation.

公开(公告)号：JPH07146804A

公开(公告)日：1995-06-06

申请号：JP14900194

申请日：1994-06-30

Applicant: TANDEM COMPUTERS INC

Inventor： MIZANUA MOHAMETSUDO RAAMAN ,  FURETSUDO SHII SABAANITSUKU ,  JIEFU EI SUPURAUSU

IPC: G06F11/22 ,  G06F11/267

Abstract: PURPOSE: To provide a diagnostic system for diagnosing the state of a circuit element capable of scanning a scannable circuit without obstructing the state of an unscannable circuit for violating the protocol of a bus to which an unscannable device is attached. CONSTITUTION: A processor interface circuit is connected through a processor bus between a microprocessor and a scannable processor circuit 24 and the scannable processor is insulated from the unscannable microprocessor 22. The processor interface circuit is also scannable and a memory element for affecting the bus by preventing scanning during the use of the bus is provided. Scanning is prevented by maintenance request signals sent from a scanning controller to the processor interface circuit and maintenance approval signals sent from the processor interface circuit to the scanning controller.

公开(公告)号：JPH07146721A

公开(公告)日：1995-06-06

申请号：JP14731794

申请日：1994-06-29

Applicant: TANDEM COMPUTERS INC

Inventor： MAAKU EI TEIRAA ,  SAMUSON KEI TOI

IPC: G01R19/165 ,  G05F1/10 ,  G05F1/56 ,  G06F1/28 ,  H03K17/22

Abstract: PURPOSE: To supply the valid instruction of the state of a supply voltage during an initial stage for applying the supply voltage by providing a supply voltage monitor and a protective circuit. CONSTITUTION: When the supply voltage Vcc reaches a first voltage level, the supply voltage monitor U1 turns on a transistor Q1. When the supply voltage Vcc reaches a second voltage level, the shunt regulator U2 of the protective circuit 14 is conducted and the voltage of a node A is lowered towards a ground potential. The open collector output of the transistor Q1 keeps the supply of a current and the transistor Q2 is not conducted because a large voltage drop is present between a resistor R3. When the supply voltage Vcc reaches a third voltage level, the monitor U1 turns off the transistor Q1. The shunt regulator U2 continues conducting, the base of the transistor Q2 is grounded and the transistor Q2 is conducted. The current flowing the resistor R6 asserts PON (power ON) signals.

公开(公告)号：JPH07141220A

公开(公告)日：1995-06-02

申请号：JP14450494

申请日：1994-06-27

Applicant: TANDEM COMPUTERS INC

Inventor： SUTEIIBUN DABURIYUU HAMIRUTON ,  UORUTAA II GIBUSON ,  CHIEN GAN KON

IPC: G06F11/22 ,  G01R31/3185

Abstract: PURPOSE: To provide a method and a device for providing the state of a scan disabled part in a scanning chain for copying and storing a registration state transferred by a scannable component to a scannable register included in scannable circuitry and allowing the observation of the registration state without the defect of an unscannable element by scanning for testing the scannable component. CONSTITUTION: A scannable logic is provided with one or more storage registers for maintaining the copy of data transmitted from a scannable unit to the register of an unscannable unit. When the scannable unit is the object of a scanning test, the register includes corresponding state information to be transferred to the unscannable unit. When the scannable and unscannable units are installed to execution conditions, the register supplies the state information to the unscannable unit so at to continue an operation.

公开(公告)号：JPH0679270B2

公开(公告)日：1994-10-05

申请号：JP5868287

申请日：1987-03-13

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F11/30

公开(公告)号：JPH0375834A

公开(公告)日：1991-03-29

申请号：JP13242490

申请日：1990-05-22

Applicant: TANDEM COMPUTERS INC

Inventor： REIMONDO SUKOTSUTO CHIYAN

IPC: G06F11/10

Abstract: PURPOSE: To improve the efficiency of a time critical path by removing a parity detector and a parity generator from the time critical path between an RAM data register and a computing element and setting those devices in parallel to the data path of the computing element. CONSTITUTION: A parity detector 100 and a parity generator 102 are set separately from a data path 112 connecting an RAM data register 106 with a computing element 110, and direct connection through the data path 112 can be attained. The parity detector 100 detects data in parallel to the computing element 110 by using the parallel data path, and therefore the delay of the processing of a data word 116 due to the computing element 110 is prevented. Thus, the speed and efficiency of sequential parity correction in the time critical path between the processors which use correctable memory sources and data is improved.