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公开(公告)号：KR1020100116413A
公开(公告)日：2010-11-01
申请号：KR1020090035100
申请日：2009-04-22
Applicant: 삼성전자주식회사
CPC classification number: G06F13/24
Abstract: PURPOSE: A reconfigurable processor and a method for handling interrupt thereof are provided to promptly process an interrupt request by securing some PE for interrupt handling when the interrupt request happens. CONSTITUTION: A CGA(Coarse-Grained Array)(101) includes plural PEs(Processing Elements), and a host processor(102) shares at least one PE with the CGA. A controller(103) designates at least one PE additionally. When an interrupt request happens while a loop operation is executed in the CGA, the controller allows the designated PE to process the interrupt request. A central register file(202) stores the processing result of the CGA and the host processor.
Abstract translation: 目的：提供可重构处理器和处理其中断的方法，以便在中断请求发生时通过保护一些PE进行中断处理来迅速处理中断请求。 构成：CGA（粗粒子阵列）（101）包括多个PE（处理元件），并且主处理器（102）与CGA共享至少一个PE。 控制器（103）另外指定至少一个PE。 当在CGA中执行循环操作时发生中断请求时，控制器允许指定的PE处理中断请求。 中央寄存器文件（202）存储CGA和主处理器的处理结果。
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公开(公告)号：KR1020100098052A
公开(公告)日：2010-09-06
申请号：KR1020090017028
申请日：2009-02-27
Applicant: 삼성전자주식회사
CPC classification number: G06F9/3836 , G06F9/327 , G06F9/30192 , G06F9/30196 , G06F9/3895 , G06F9/3897 , G06F9/4887 , G06F9/4893
Abstract: PURPOSE: An interrupt handling apparatus and method for an equal-model processor, and a processor including the interrupt handling apparatus are provided to promptly process an interrupt by processing an interrupt in the processor. CONSTITUTION: A remaining latency updater(14) compares a current latency with a residual latency. If the current latency is larger than the residual latency, the residual latency updating unit updates the residual latency to the value of the current latency. An interrupt support determiner(16) outputs a signal for indicating the interrupt support based on the residual latency. If the residual latency is larger than 1, the interrupt support determination unit outputs an interrupt non-support flag.
Abstract translation: 目的：提供一种用于等模型处理器的中断处理装置和方法，以及包括中断处理装置的处理器，通过处理处理器中的中断来及时处理中断。 构成：剩余的延迟更新器（14）将当前延迟与剩余延迟进行比较。 如果当前延迟大于剩余延迟，则剩余延迟更新单元将剩余延迟更新为当前等待时间的值。 中断支持确定器（16）基于剩余延迟输出用于指示中断支持的信号。 如果剩余延迟大于1，则中断支持确定单元输出中断非支持标志。
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公开(公告)号：KR100813662B1
公开(公告)日：2008-03-14
申请号：KR1020060113588
申请日：2006-11-17
Applicant: 삼성전자주식회사
IPC: G06F15/177 , G06F9/455 , G06F15/00
CPC classification number: G06F8/443 , G06F17/5045 , G06F2217/68
Abstract: A profiler for optimizing architecture and application of a processor is provided to offer information needed for considering/optimizing a program and an application specific architecture processor in addition to the information for optimizing the program to a target processor. An architecture analyzer(231) generates architecture analysis information by analyzing architecture description(211) describing architecture of an application specific architecture processor including a plurality of PEs(Processing Elements). A static analyzer(232) generates static analysis information(222) by analyzing program static information describing static information of the program. A dynamic analyzer(233) generates dynamic analysis information(223) by analyzing program dynamic information describing dynamic information generated by simulating the program. A cross profiling analyzer(234) generates the information for optimizing the application specific architecture processor executing the program based on at least one of architecture, static, and dynamic analysis information. The architecture analyzer includes an operation analyzer generating operation group information for the PEs by analyzing the architecture description.
Abstract translation: 提供用于优化处理器的架构和应用的分析器，以提供除了用于将目标处理器优化程序的信息之外的用于考虑/优化程序和应用特定架构处理器所需的信息。 架构分析器（231）通过分析描述包括多个PE（处理元件）的应用专用架构处理器的架构的架构描述（211）来生成架构分析信息。 静态分析器（232）通过分析描述程序的静态信息的程序静态信息来生成静态分析信息（222）。 动态分析器（233）通过分析描述通过模拟程序生成的动态信息的程序动态信息来生成动态分析信息（223）。 交叉分析分析器（234）基于架构，静态和动态分析信息中的至少一个生成用于优化执行该程序的应用专用架构处理器的信息。 架构分析器包括通过分析架构描述来生成用于PE的操作组信息的操作分析器。
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公开(公告)号：KR100812346B1
公开(公告)日：2008-03-11
申请号：KR1020060011200
申请日：2006-02-06
Applicant: 삼성전자주식회사
IPC: G06F9/48
CPC classification number: H03K19/177 , G06F9/4812
Abstract: 재구성 어레이의 동작 중 인터럽트 요청이 발생하면, 상기 재구성 어레이의 동작을 정지(pause)하는 단계, 상기 인터럽트 요청의 처리에 사용될 레지스터의 값을 저장하는 단계, 상기 인터럽트 요청에 대한 인터럽트 서비스를 수행하는 단계 및 상기 레지스터의 값을 복구하고, 상기 재구성 어레이의 동작을 재개(resume)하는 단계를 포함하는 재구성 어레이에서의 인터럽트 처리 방법이 제공된다.
코어스 그레인 어레이(coarse grained array), 재구성 아키텍처{reconfigurable architecture}, 인터럽트{interrupt}-
公开(公告)号：KR1020070118543A
公开(公告)日：2007-12-17
申请号：KR1020070056631
申请日：2007-06-11
Applicant: 삼성전자주식회사
Abstract: A method and a device for performing multitasking in a reconfigurable array are provided to enable the reconfigurable array to quickly complete the multitasking for a plurality of reconfiguring operations by recovering only the unique information of a CPU in a time point when a main process is stopped and quickly performing the main process again. A unique memory(350) stores the unique information in response to a first control signal. A controller(340) verifies whether the reconfigurable operation is a main controlling process and generates a second control signal in response to a verification result. The reconfigurable array(310) receives a request for performing one reconfigurable operation during another reconfigurable operation, stops the reconfigurable operation and keeps the unique information of peripheral processors in response to the first control signal. The reconfigurable array receives the request for performing one reconfigurable operation during another reconfigurable operation, recovers the unique information of the CPU in response to the second control signal, and restarts the main processing operation.
Abstract translation: 提供了一种用于在可重配置阵列中执行多任务的方法和设备，以使得可重构阵列能够通过在主进程停止的时间点仅恢复CPU的唯一信息来快速完成多重重新配置操作的多任务处理， 再次快速执行主流程。 唯一存储器（350）响应于第一控制信号存储唯一信息。 控制器（340）验证可重构操作是否是主控制过程，并且响应于验证结果生成第二控制信号。 可重配置阵列（310）在另一可重新配置的操作期间接收执行一个可重构操作的请求，停止可重新配置的操作，并响应于第一控制信号保持外围处理器的唯一信息。 可再配置阵列在另一可重构操作期间接收执行一个可重构操作的请求，响应于第二控制信号恢复CPU的唯一信息，并且重启主处理操作。
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Patent Agency Ranking
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公开(公告)号：KR101782373B1
公开(公告)日：2017-09-29
申请号：KR1020100111743
申请日：2010-11-10
Applicant: 삼성전자주식회사
CPC classification number: G06T1/60
Abstract: 적어도두 개의축을갖는다차원공간에기초하여주소공간이정의되는메모리부, 및두 개의축 중에서제 1 축에대응되는행(row)을가리키는제 1 포인터가저장되는제 1 포인터레지스터, 및두 개의축 중에서제 2 축에대응되는열(column)을가리키는제 2 포인터가저장되는제 2 포인터레지스터를포함하는메모리접근부를포함하는 XY 스택메모리를이용한컴퓨팅장치가제공된다.
Abstract translation: 一种存储单元，其中基于具有至少两个轴的维度空间来定义地址空间，以及第一指针寄存器，其中存储指示与所述两个轴中的第一轴对应的行的第一指针， 以及第二指针寄存器，其中指示对应于两个轴的列的第二指针被存储在XY堆栈存储器中。
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公开(公告)号：KR101744150B1
公开(公告)日：2017-06-21
申请号：KR1020100125074
申请日：2010-12-08
Applicant: 삼성전자주식회사
IPC: G06F15/167 , G06F15/80 , G06F13/16 , G06F11/22
CPC classification number: G06F15/167
Abstract: 멀티프로세서시스템의지연관리기술을개시한다. 메모리를공유하는멀티프로세서시스템에지연관리장치를설치하고, 이를통해각 프로세서또는공유메모리로부터발생하는지연신호검출시, 멀티프로세서시스템의각 프로세서의동작지연을효율적으로관리함으로써시스템성능을향상시킬수 있다.
Abstract translation: 公开了一种多处理器系统的延迟管理技术。 可以通过在多处理器系统用于共享存储器，并通过其管理各处理器的操作延迟为每个处理器提供延时管理装置提高了系统的性能，或者以延迟从共享存储器多处理器系统所得到的检测信号高效率地 。
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公开(公告)号：KR101699685B1
公开(公告)日：2017-01-26
申请号：KR1020100114045
申请日：2010-11-16
Applicant: 삼성전자주식회사
CPC classification number: G06F9/30036 , G06F9/3017 , G06F9/30192 , G06F9/3887
Abstract: 다수의명령어오퍼랜드중 하나의명령어오퍼랜드를선택하는선택부로입력되는명령어오퍼랜드의개수를줄임으로써, 선택부의구조를단순화할수 있는명령어오퍼랜드변경장치및 방법이개시된다. 명령어오퍼랜드변경장치는제 1 명령어오퍼랜드들및 제 2 선택부로입력되는제 2 명령어오퍼랜드들중 적어도하나를선택하고, 상기선택된명령어오퍼랜드의입력경로및 선택된명령어오퍼랜드종류중 적어도하나를변경할수 있다.
Abstract translation: 提供了一种用于修改指令操作数的装置和方法。 该装置包括被配置为接收第一指令操作数的第一选择器和被配置为接收第二指令操作数的第二选择器。 该装置还包括：修改单元，被配置为选择第一指令操作数和第二指令操作数，并且修改所选择的第一指令操作数和所选择的第二指令操作数，以减少输入到第一选择器和第二选择器的操作数指令 。
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