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公开(公告)号：KR1019960006472B1
公开(公告)日：1996-05-16
申请号：KR1019930028669
申请日：1993-12-20
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: in order for a host to use function of a fiber distributed data interface (FDDI) through an input/output processor, sending a M_FDDI message to a controller of a system and driving one like fddiio of firmware functions to pager a related function according to a FDDI packet commander word; operating the FDDI packet commander word; accessing RAM of a board by a RAM driving unit having a SMT function; separating the RAM driving from a detailed hardware like a VME bus address, interrupt level, and interrupt vector; operating the SMT functions; if communication protocol is downloaded by the user's processor, controlling access to the RAM and also controlling the input/output of the data and the input/output characteristic of the FDDI controller; if the data of the FDDI controller is received from the hoster, using a vector interrupt of the VEM bus; and if the data of the FDDI is received from the host to process the data from the host and FDDI controller, using the vector interrupt of the VEM bus.
Abstract translation: 为了使主机通过输入/输出处理器使用光纤分布式数据接口（FDDI）的功能，将M_FDDI消息发送到系统的控制器并且驱动类似于固件功能的fddiio的功能，以根据 FDDI数据包指令字; 操作FDDI数据包指令字; 通过具有SMT功能的RAM驱动单元访问电路板的RAM; 将RAM驱动与诸如VME总线地址，中断级别和中断向量的详细硬件分离; 操作SMT功能; 如果通信协议由用户的处理器下载，则控制对RAM的访问，并且还控制数据的输入/输出以及FDDI控制器的输入/输出特性; 如果从主机接收到FDDI控制器的数据，则使用VEM总线的向量中断; 并且如果从主机接收到来自主机和FDDI控制器的数据来处理FDDI的数据，则使用VEM总线的向量中断。
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公开(公告)号：KR1019950022412A
公开(公告)日：1995-07-28
申请号：KR1019930028669
申请日：1993-12-20
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: 본 발명은 고속 중형 컴퓨터에 고속 근거리 통신망을 제공하기 위해 고속 중형 컴퓨터와 유사한 입출력 구조를 가진 TICOM의 IOP에 펌웨어로 구성하여 동작시키는 방법에 관한 것이다. FDDIIOP 펌웨어 구동기는 고속 근거리 통신을 실현하기 위해 TICOM의 입출력 전용 처리기에 FDDI를 접속하여 동작하는 펌웨어 구동기이다. TICOM의 컴퓨터 통신에서 호스트 시스템간의 물리적인 접속은 통신 전용 입출력 처리기에 확장된 VME버스에 연결되며, 호스트에서 FDDI IOP 펌웨어를 호출하는 FDDI 호스트 구동기를 거쳐 상위 프로토콜인 TCP/IP와 상호 접속하는 단계를 거치게 된다. 그리고 본 발명은 호스트 CUP상에서 동작하는 FDDI 구동기가 시스템버스에 연결된 입출력 제어기의 FDDI 펌웨어 구동기에게 입출력을 요구할 경우 FDDI 펌웨어 구동기는 시스템 제어기와 VME 버스를 통해 상호 동작하여 상위층의 응용 프로토콜에게 데이타의 입출력 동작을 수행하여 통신할 수 있게 된다.
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Patent Agency Ranking
公开(公告)号：KR1019950002163B1
公开(公告)日：1995-03-14
申请号：KR1019920015844
申请日：1992-09-01
Applicant: 한국전자통신연구원
IPC: G06F9/00
Abstract: The hangul validation suite (HVS) verifying the kernel routines, commands, C-libraries, and curse libraries to confirm functional stabilities and find statistical data includes the first step checking environment for the HVS; the second step stopping the HVS to print the required environment when the HVS is not in proper environment; the third step generating the required data structure and storing the related data to the disk files when the HVS is in proper environment; the fourth step finding whether the validation mode is in the individual checking mode or the global checking mode; the fifth step calling the individual validation script for the individual checking mode; the sixth mode calling the multiple individual validation scripts for the global checking mode in sequence; the seventh step assessing the testing results; the final step generating the statistical data.
Abstract translation: 验证套件（HVS）验证内核例程，命令，C库和诅咒库以确认功能稳定性并查找统计数据包括HVS的第一步检查环境; 第二步，在HVS不适当的环境下，停止HVS打印所需的环境; 第三步产生所需的数据结构，并且当HVS处于适当的环境时，将相关数据存储到磁盘文件; 第四步，确定验证模式是否处于单独检查模式或全局检查模式; 第五步调用单独验证脚本进行单独检查模式; 第六种模式按顺序调用全局检查模式的多个单独验证脚本; 评估测试结果的第七步; 生成统计数据的最后一步。
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公开(公告)号：KR1019940006836B1
公开(公告)日：1994-07-28
申请号：KR1019910019578
申请日：1991-11-05
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The method avoiding the bottle neck problem by reducing the number of interrupts has the initializing step initializing the communication media on each slot. A channel header having are exclusive slot number is attached on the message. The requested processor interrupts the target slot when the number of messages and timeout condition meet. The target slot receives the interrupt request and checks the vector file to assign interrupt class, transmitting/receiving slot numbers and channel numbers to call the interrupt handler.
Abstract translation: 通过减少中断次数避免瓶颈问题的方法是初始化步骤，在每个插槽上初始化通信介质。 具有独占时隙号的信道报头被附加在消息上。 当消息数量和超时条件满足时，请求的处理器中断目标时隙。 目标时隙接收中断请求，并检查向量文件以分配中断类，发送/接收槽号和通道号以调用中断处理程序。
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公开(公告)号：KR1019930005844B1
公开(公告)日：1993-06-25
申请号：KR1019900017338
申请日：1990-10-29
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The device for transmitting the control signal and the data simultaneously through the set pass comprises: a tag interpretation circuit (1) outputting the signal for a pass setting; an overlap demanding inhibit circuit (2) sending the line connecting signal and the blocking signal; a pass status storing circuit (3) storing the present set pass status by inputting the reset signal and the clock signal; an auxiliary control signal circuit (4) transfering the answer signal, the blocking signal and the control signal to the input/output port; a pass control circuit (5) controlling the connecting status of the input/output port by outputting the control signal.
Abstract translation: 用于通过设定通过同时发送控制信号和数据的装置包括：标签解释电路（1），输出用于通过设置的信号; 重叠要求禁止电路（2）发送线路连接信号和阻塞信号; 通过状态存储电路（3），通过输入复位信号和时钟信号来存储当前的设定通过状态; 辅助控制信号电路（4）将应答信号，阻塞信号和控制信号传送到输入/输出端口; 通过控制电路（5），通过输出控制信号来控制输入/输出端口的连接状态。
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公开(公告)号：KR1019920003286B1
公开(公告)日：1992-04-27
申请号：KR1019890019673
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: Synchronizing clock pulses are generated by a central slot (12) so as to be supplied through signal lines of a back plane (11). Two outer slots (13)(14) and (15)(16) which are adjacent to each other, and which are located outwardly from the central slot (12) are electrically bundled together as groups. The lengths of the signal lines of the back plane (11), which connect the groups to the central slot (12), are made to be the same, so that bus clocks of the central slot (12) should reach the groups simultaneously. The method simplifys the circuit constitution, to facilitate a serial termination, and minimizes the load of the signal receiving end.
Abstract translation: 同步时钟脉冲由中心槽（12）产生，以便通过背板（11）的信号线提供。 彼此相邻并从中心狭槽（12）向外定位的两个外槽（13）（14）和（15）（16）被组合在一起。 将组合到中心狭槽（12）的背板（11）的信号线的长度相同，使得中心槽（12）的总线时钟同时到达组。 该方法简化了电路结构，便于串行终端，并使信号接收端的负载最小化。
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