公开(公告)号：AU2003292268A1

公开(公告)日：2004-06-23

申请号：AU2003292268

申请日：2003-11-14

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.

公开(公告)号：DE69910860D1

公开(公告)日：2003-10-09

申请号：DE69910860

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of processors and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the tag is valid and that the first data item is invalid. Thereafter, the interconnect is snooped to detect a data transfer initiated by another of the plurality of caches, where the data transfer is associated with the address indicated by the address tag and contains a valid second data item. In response to detection of such a data transfer while the coherency indicator is set to the first state, the first data item is replaced by storing the second data item in the first cache in association with the address tag. In addition, the coherency indicator is updated to a second state indicating that the second data item is valid and that the first cache can supply said second data item in response to a request.

公开(公告)号：DE69908204D1

公开(公告)日：2003-07-03

申请号：DE69908204

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A data processing system and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of caches and a plurality of processors grouped into at least first and second clusters, where each of the first and second clusters has at least one upper level cache and at least one lower level cache. According to the method, a first data item in the upper level cache of the first cluster is stored in association with an address tag indicating a particular address. A coherency indicator in the upper level cache of the first cluster is set to a first state that indicates that the address tag is valid and that the first data item is invalid. Similarly, in the upper level cache of the second cluster, a second data item is stored in association with an address tag indicating the particular address. In addition, a coherency indicator in the upper level cache of the second cluster is set to the first state. Thus, the data processing system implements a coherency protocol that permits a coherency indicator in the upper level caches of both of the first and second clusters to be set to the first state.

公开(公告)号：ES2186708T3

公开(公告)日：2003-05-16

申请号：ES95480127

申请日：1995-09-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  KAISER JOHN MICHAEL

IPC: G06F13/362 ,  G06F15/16 ,  G06F13/364 ,  G06F15/177

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

公开(公告)号：AU2002319498A1

公开(公告)日：2003-02-17

申请号：AU2002319498

申请日：2002-07-25

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  GUTHRIE GUY LYNN ,  LEWIS JERRY DON ,  JOYNER JODY BERN

IPC: H04L12/42 ,  G06F15/17 ,  G06F15/173

Abstract: The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.

公开(公告)号：CZ9903604A3

公开(公告)日：2000-07-12

申请号：CZ360499

申请日：1998-04-03

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  KAISER JOHN MICHAEL ,  LEWIS JERRY DON

IPC: G06F12/0806 ,  G06F12/08

公开(公告)号：SG73505A1

公开(公告)日：2000-06-20

申请号：SG1998000657

申请日：1998-03-30

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK-EDWARD

IPC: G06F12/08 ,  G06F13/16

公开(公告)号：PL336162A1

公开(公告)日：2000-06-05

申请号：PL33616298

申请日：1998-04-03

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  KAISER JOHN MICHAEL ,  LEWIS JERRY DON

IPC: G06F12/08 ,  G06F12/0831

公开(公告)号：SG71772A1

公开(公告)日：2000-04-18

申请号：SG1998000675

申请日：1998-03-31

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAM DEREK EDWARD

IPC: G06F12/08

Abstract: Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable.

公开(公告)号：CA2260285A1

公开(公告)日：1999-08-17

申请号：CA2260285

申请日：1999-01-25

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN

IPC: G06F12/08 ,  G06F13/20

Abstract: A modified MESI cache coherency protocol is implemented within a level two (L2) cache accessible to a processor having bifurcated level one (L1) data and instruction caches. The modified MESI protocol includes two substates of the shared state, which denote the same coherency information as the shared state plus additional information regarding the contents/coherency of the subject cache entry. One substate, S IC0, indicates that the cache entry is assumed to contain instructions since the contents were retrieved from system memory as a result of an instruction fetch operation. The second substate, S IC1, indicates the same information plus that a snooped flush operation hit the subject cache entry while its coherency was in the first shared substate. Deallocation of a cache entry in the first substate of the shared coherency state within lower level (e.g., L3) caches does not result in the contents of the same cache entry in an L2 cache being invalidated. Once the first substate is entered, the coherency state does not transition to the invalid state unless an operation designed to invalidate instructions is received. Operations from a local processor which contravene the presumption that the contents comprise instructions may cause the coherency state to transition to an ordinary shared state. Since the contents of a cache entry in the two coherency substates are presumed to be instructions, not data, instructions within an L2 cache are not discarded as a result of snooped flushes, but are retained for possible reloads by a local processor.