公开(公告)号：DE69125542T2

公开(公告)日：1997-09-25

申请号：DE69125542

申请日：1991-07-26

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  SCHEUERLEIN ROY E

IPC: G11C11/409 ,  G11C11/4091

Abstract: A dynamic random access memory comprises a sense amplifier including a latch (10) comprising a pair of NMOS FETs (TN1,TN2) with their gates and drains cross coupled and with their sources connected to a common node. A pair of bitlines (BL,BLN) are coupled to the cross coupled nodes of the latch (10). An FET (TP5) enables the bitlines to be precharged to a precharge voltage. A latch driving circuit (16) is coupled to the common node of the latch (10). The latch driving circuit (16) comprises means (TN5,TN6) for coupling a reference voltage to the common node for activating the latch (10) after the bitlines have been precharged, and means (TN7,20) for controlling the voltage of the common node in such a manner that the downward voltage swing of the lower level bitline towards the reference voltage, produced by activation of the latch (10), is limited to a predetermined voltage level higher than the reference voltage. This advantageously provides a high speed memory operation and reduced power consumption.

公开(公告)号：DE112012004439T5

公开(公告)日：2014-07-17

申请号：DE112012004439

申请日：2012-09-13

Applicant: IBM

Inventor： CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  ROBSON NORMAN W ,  ROSENBLATT SAMI ,  FAINSTEIN DANIEL J ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/00

Abstract: Eine Erzeugung einer zufälligen intrinsischen Chip-ID verwendet eine Speicherfehlersignatur. Eine 1. und eine 2. ID werden unter Verwendung von Testeinstellungen erzeugt, wobei eine 1. Einstellung restriktiver als die 2. ist und in der ersten ID-Bitzeichenkette 275, welche die 2. ID-Bitzeichenkette 290 enthält, mehr Fehler erzeugt werden. Eine Speicherpausenzeit-Steuerung steuert eingestellt durch eine BIST-Engine 625 die Anzahl von Speicherfehlern, wobei die Fehleranzahlen 803, 920 ein vorgegebenes Fehlerziel erfüllen. Eine Überprüfung bestätigt, ob die 1. ID die 2. ID-Bitzeichenkette enthält, wobei es sich bei der ID um die für die Authentifizierung verwendete handelt. Die Authentifizierung wird durch eine 3. ID mit einer derartigen Zwischenbedingung ermöglicht, dass die 1. ID die 3. ID-Bitzeichenkette enthält und die 3. ID die 2. ID-Bitzeichenkette enthält. Die Zwischenbedingung enthält ein Wächterband, um ein Bitinstabilitätsproblem nahe der 1. und 2. ID-Grenze zu beseitigen. Die Zwischenbedingung wird bei jedem ID-Lesevorgang geändert, was zu einer sichereren Identifikation führt.

公开(公告)号：GB2509823A

公开(公告)日：2014-07-16

申请号：GB201320411

申请日：2013-11-19

Applicant: IBM

Inventor： ROSENBLATT SAMI ,  KIRIHATA TOSHIAKI ,  CHELLAPPA SRIVATSAN ,  IYER SUBRAMANIAN

IPC: G06F21/44

Abstract: The present invention provides an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine 104, a self-test engine 106, and an intrinsic component 108. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using at least the intrinsic feature, and stores the authentication value in memory. A second authentication value is then generated using at least an authentication challenge 130. The identification engine includes a compare circuitry 116 that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

公开(公告)号：DE69833415T2

公开(公告)日：2006-09-21

申请号：DE69833415

申请日：1998-09-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C7/06 ,  G11C11/403 ,  G11C5/02 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. A master data line (MDQ) switch is located in a sense amplifier region occupying a corresponding row-wise space to at least one driver to provide space efficient placement thereof.

公开(公告)号：DE69831294T2

公开(公告)日：2006-06-08

申请号：DE69831294

申请日：1998-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C7/06 ,  G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

公开(公告)号：DE69831294D1

公开(公告)日：2005-09-29

申请号：DE69831294

申请日：1998-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/06

Abstract: The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

公开(公告)号：MY117880A

公开(公告)日：2004-08-30

申请号：MYPI9800853

申请日：1998-02-26

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C7/00 ,  G11C29/04 ,  G11C29/00

Abstract: A VARIABLE SIZE REDUNDANCY REPLACEMENT (VSRR) ARRANGEMENT FOR MAKING A MEMORY (10) FAULT-TOLERANT. A REDUNDANCY ARRAY (130) SUPPORTING THE MEMORY INCLUDES A PLURALITY OF VARIABLE SIZE REDUNDANCY UNITS (RU0 - RU15), EACH OF WHICH ENCOMPASSES A PLURALITY OF REDUNDANCY ELEMENTS. THE REDUNDANCY UNITS, USED FOR REPAIRING FAULTS IN THE MEMORY, ARE INDEPENDENTLY CONTROLLED. ALL THE REDUNDANCY ELEMENTS WITHIN A REPAIR UNIT ARE PREFERABLY REPLACED SIMULTANEOUSLY. THE REDUNDANCY ELEMENTS IN THE REDUNDANCY UNIT ARE CONTROLLED BY DECODING ADDRESS LINES. THE VARIABLE SIZE THAT CHARACTERIZES THIS CONFIGURATION MAKES IT POSSIBLE TO CHOOSE THE MOST EFFECTIVE REDUNDANCY UNIT, AND IN PARTICULAR, THE ONE MOST CLOSELY FITTING THE SIZE OF THE CLUSTER OF FAILURES TO BE REPLACED. THIS CONFIGURATION SIGNIFICANTLY REDUCES THE OVERHEAD CREATED BY ADDED REDUNDANCY ELEMENTS AND CONTROL CIRCUITRY, WHILE IMPROVING THE ACCESS SPEED AND REDUCING POWER CONSUMPTION. FINALLY, A FAULT-TOLERANT BLOCK REDUNDANCY CONTROLLED BY A PRIORITY DECODER MAKES IT POSSIBLE TO USE VSRR UNITS FOR REPAIRING FAULTS IN THE BLOCK REDUNDANCY PRIOR TO ITS USE FOR REPLACING A DEFECTIVE BLOCK WITHIN THE MEMORY. (FIG. 2)

公开(公告)号：DE69822280D1

公开(公告)日：2004-04-15

申请号：DE69822280

申请日：1998-12-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SAi), at least one pair of master bitlines (MBLi, MBLi) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL1i, LBL1i, LBL2i, LBL2i), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.

公开(公告)号：DE10315049A1

公开(公告)日：2003-10-30

申请号：DE10315049

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C5/02

Abstract: The computer memory storage field (501) has first and second storage cell banks (510a,b) with zigzag edges (531,532). Blank or unused edges lie adjacent to each other. Each memory cell bank incorporates a memory block (330a,b). The system includes drivers (140a,b) for horizontal word lines (WL). Bit lines (BL) on the zigzag edges are arranged in pairs (BL-Paar) and cross each other (334) at intervals. The memory cells (331) consist of transistors.

公开(公告)号：DE69911364D1

公开(公告)日：2003-10-23

申请号：DE69911364

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.