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公开(公告)号：DE69628908D1
公开(公告)日：2003-08-07
申请号：DE69628908
申请日：1996-04-05
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , FONTANA MARCO
Abstract: The present invention relates to a voltage regulator (1) for the programming of electrically programmable non-volatile memory cells in a cells matrix divided in segments with said regulator being the type comprising an amplifier stage (2) connected and powered between a first (Vpp) and a second reference voltage (GND) and having: a first input terminal (+) connected to a divider (3) of the first reference voltage (Vpp), an output terminal (U) connected to the control terminal of a MOS transistor (Mu) which has a conduction terminal connected to the memory cells through a programming line (6), a second input terminal (-) connected in feedback to said programming line (6), and an input circuit portion (8) made up of active elements and inserted in turn between said reference voltages (Vpp,GND). This portion (8) is active on the connection between the amplifier (2) and the first reference voltage (Vpp) in response to at least one pair of signals (PG,DI) to activate the regulator only when there is at least one cell to be programmed in the segment associated with the regulator. Specifically, the above mentioned input circuit portion (8) is made up of a complementary pair of transistors (Pin,Min) and at least one enablement transistor (M2) with there being applied to the complementary pair a first programming enablement signal (PG) and to the transistor (M2) there being applied a second signal (DI) indicating the presence of a bit to be programmed.
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公开(公告)号：DE69626827D1
公开(公告)日：2003-04-24
申请号：DE69626827
申请日：1996-10-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: The invention relates to a protection circuit (1) for electrically programmable non-volatile memory cells, comprising: at least one control circuit (5), being connected between first (Vdd) and second (GND) voltage references and having at least an input terminal (I3) and an output terminal (O4), the output terminal (O4) delivering a reading/programming voltage signal (UGV) to the cells; and at least one control circuit (4) having a first input terminal (I5) for receiving an enabling control signal (FUSE_cnt), a second input terminal (I6) for receiving a Power-on-Reset signal (POR), and an output terminal (O2) for supplying a control signal (CNT) to the first input terminal (I3) of the control circuit (5). The protection circuit (1) of this invention further comprises: a disabling circuit (3), being connected between the first (Vdd) and the second voltage reference (GND) and having an output terminal (O1) connected to the first input terminal (I3) of the control circuit (5), which comprises at least one redundant memory element (M1) connected between a translated voltage reference (DIS) and the second voltage reference (GND).
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公开(公告)号：DE69624785D1
公开(公告)日：2002-12-19
申请号：DE69624785
申请日：1996-02-05
Applicant: ST MICROELECTRONICS SRL
Inventor： FONTANA MARCO , PASCUCCI LUIGI
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公开(公告)号：DE69616747T2
公开(公告)日：2002-08-08
申请号：DE69616747
申请日：1996-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
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公开(公告)号：DE69619358D1
公开(公告)日：2002-03-28
申请号：DE69619358
申请日：1996-04-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: A redundancy memory register for storing defective addresses of defective memory elements in a memory device comprises a plurality of memory units (MU0-MU10) each one storing a respective defective address bit and comparing the defective address bit stored therein with a respective current address bit (RA0-RA10) of a current address supplied to the memory device. The register comprises a first group (G1) of memory units (MU4-MU10) and a second group (G2') of memory units (MU0-MU3) storing a first defective address, and a third group (G2'') of memory units (MU0-MU3) storing, together with the first group, a second defective address which has an address part (RA4-RA10) in common with the first defective address. The first and second group of memory units supply first redundancy selection means (15,16,18,SW1,DA) for selecting a first redundancy memory element (RWA) when the current address coincides with the first defective address. The first and third group of memory units supply second redundancy selection means (17,18,SW2,DB) for selecting a second redundancy memory element (RWB) when the current address coincides with the second defective address. The register comprises first address configuration detection means (1) for detecting if the current address coincides with a default configuration stored in the first and second group of memory units and for correspondingly deactivating the first and second redundancy selection means, and second address configuration detection means (2) for detecting if the current address coincides with a default configuration stored in the third group of memory units and for consequently deactivating the second redundancy selection means.
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Patent Agency Ranking
公开(公告)号：DE69618928D1
公开(公告)日：2002-03-14
申请号：DE69618928
申请日：1996-04-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
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公开(公告)号：DE69617919D1
公开(公告)日：2002-01-24
申请号：DE69617919
申请日：1996-06-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: A semiconductor memory device comprising redundancy memory elements for functionally replacing defective memory elements, redundancy circuits (6,7) for operating said functional substitution of the redundancy memory elements for the defective memory elements, and operation mode control circuits (13) for controlling the memory device to operate accoriding to a plurality of operation modes, said plurality of operation modes comprising a memory read mode and redundancy test modes for testing the redundancy circuits. The memory device comprises an internal shared bus (IB) of signal lines that when the memory device is operated in said read mode is used to transfer read data signals (RDAT) to output terminals (OB,I/O) of the memory device and when the memory device is operated in one of said redundancy test modes is used to transfer redundancy signals (RCOL,RROW,RCNT,FTS), depending on the redundancy test mode, to the output terminals of the memory device.
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公开(公告)号：DE69521493D1
公开(公告)日：2001-08-02
申请号：DE69521493
申请日：1995-04-04
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected in an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.
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公开(公告)号：IT1305118B1
公开(公告)日：2001-04-10
申请号：ITTO980840
申请日：1998-10-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C8/18
Abstract: An address transition detector in a semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit comprising bistable memory circuits for storing the values of the address transition signals at each logical status changement of the adddress signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals. According to the present invention, said monostable circuit (123; 223; 303; 403) has breaking means (140; 240; 340; 440) of the feedback path (FB) in response to an enable signal (AE).
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公开(公告)号：DE69424523T2
公开(公告)日：2001-01-18
申请号：DE69424523
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO , GOLLA CARLA MARIA
Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.
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