Abstract:
A wireless device for processing streams of media data in a wireless bi-directional communications network. The bi-directional communications network is capable of transmitting and receiving media data streams which comprise a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information. The wireless device has at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (110), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifying one of a plurality of data element sizes, and to write concatenated results in the register file.
Abstract:
A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
Abstract:
A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
Abstract:
A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
Abstract:
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.
Abstract:
A method of printing a sub-resolution device feature (16) having first and second edges spaced in close proximity to one another on a semiconductor substrate (20) includes the steps of first depositing a radiation-sensitive material on the substrate, then providing a first mask image segment (11) which corresponds to the first edge. The first mask image segment is then exposed with radiation (10) using an imaging tool (12) to produce a first pattern edge gradient (14). The first pattern edge gradient defines the first edge of the feature in the material. A second mask image segment (13) is then provided corresponding to the second feature edge. This second mask image segment is exposed to radiation (10) to produce a second pattern edge gradient (17) which defines the second edge of the feature. Once the radiation-sensitive material has been developed, the two-dimensional feature is reproduced on the substrate.
Abstract:
Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
Abstract:
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract:
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract:
A system and method expands a source operand to a width greater than that of a general purpose register or a data path. Operands are provided substantially larger than the data path width of a processor. The general purpose register specifies a memory address from which several data path widths of data are read. A data path functional unit is augmented with dedicated storage to which the memory operand is copied on initial execution of the instruction. Further instructions specifying the same memory address read the dedicated storage to obtain the operand value, upon verification that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch is combined with register operands in the functional unit, producing a result the size of a general register, so no dedicated storage is required for the result.