中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

538 records (took 0.037 seconds)

    METHOD FOR TRANSFERRING GRAPHENE
    101.
    发明公开
    METHOD FOR TRANSFERRING GRAPHENE 审中-公开
    VERFAHREN ZURÜBERTRAGUNGVON GRAPHEN

    公开(公告)号：EP3135631A1

    公开(公告)日：2017-03-01

    申请号：EP15382430.5

    申请日：2015-08-24

    Applicant: Graphenea, S.A.

    Inventor： ZURUTUZA ELORZA, Amaia ,  CENTENO PÉREZ, Alba

    IPC: B81C1/00

    CPC classification number: B81C1/00158 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/0191 ,  B81C2201/053 ,  C01B32/194

    Abstract: A method of transferring graphene onto a target substrate having cavities and/or holes or onto a substrate having at least one water soluble layer is disclosed. It comprises the steps of: applying a protective layer (4) onto a sample comprising a stack (20) formed by a graphene monolayer (2) grown on a metal foil or on a metal thin film on a silicon substrate (1); attaching to said protective layer (4) a frame (5) comprising at least one outer border and at least one inner border, said frame (5) comprising a substrate and a thermal release adhesive polymer layer, the frame (5) providing integrity and allowing the handling of said sample; removing or detaching said metal foil or metal thin film on a silicon substrate (1); once the metal foil or metal thin film on a silicon substrate (1) has been removed or detached, drying the sample; depositing the sample onto a substrate (7); removing said frame (5) by cutting through said protective layer (4) at said at least one inner border of the frame (5) or by thermal release.

    Abstract translation: 公开了一种将石墨烯转移到具有空穴和/或孔的目标基底上或具有至少一个水溶性层的基底上的方法。 其包括以下步骤：将保护层（4）施加到包含由在金属箔上生长的石墨烯单层（2）或在硅衬底（1）上的金属薄膜上形成的堆叠（20）的样品上; 附接到所述保护层（4）的框架（5）包括至少一个外边界和至少一个内边界，所述框架（5）包括基底和热释放粘合剂聚合物层，所述框架（5）提供完整性和 允许处理所述样品; 在硅衬底（1）上移除或分离所述金属箔或金属薄膜; 一旦硅衬底（1）上的金属箔或金属薄膜已经被去除或分离，干燥样品; 将样品沉积到衬底（7）上; 通过在框架（5）的所述至少一个内边界处切割所述保护层（4）或通过热释放来移除所述框架（5）。

    Integrated circuit with MEMS element designed to avoid sticking and manufacturing method thereof
    103.
    发明公开
    Integrated circuit with MEMS element designed to avoid sticking and manufacturing method thereof 审中-公开
    集成电路与MEMS元件设计，以避免其粘附和制造方法

    公开(公告)号：EP2695848A1

    公开(公告)日：2014-02-12

    申请号：EP12180166.6

    申请日：2012-08-10

    Applicant: NXP B.V.

    Inventor： Lander, Robert

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/0018 ,  B81C1/00134 ,  B81C1/00928 ,  B81C2201/0133 ,  B81C2203/0136 ,  B81C2203/0145

    Abstract: An integrated circuit is disclosed comprising a MEMS (microelectromechanical system) element (10) in a plane of the integrated circuit, the MEMS element being suspended in a cavity (160) over a substrate (100), said cavity including a first cavity region (20) in said plane spatially separating an edge of the MEMS element from a wall section (12) of the cavity, said edge being arranged to be displaced relative to the wall section; and a second cavity region (30) in said plane forming part of a fluid path further including the first cavity region, said fluid path defining a first volume; and a third cavity region (34) in said plane defining a second volume in fluid connection with the second cavity region, wherein the maximum width of the second cavity region is larger than the maximum width of the third cavity region, the second and third cavity regions having maximum widths that are larger than the maximum width of the first cavity region, and wherein at least a part of the second volume is excluded from the fluid path.

    Abstract translation: 上集成电路计划盘游离缺失，其包括在该集成电路的MEMS（微机电系统）元件（10），所述MEMS元件悬挂在在基片的空腔（160）（100），所述腔体包括第一腔区域（ 20）所述计划在从腔的壁部（12）的MEMS元件的边缘在空间上分离，所述边缘被布置相对于壁部分被移位; 和第二腔区域（30）的平面内成形进一步包括在第一腔室区域的流体路径的一部分，所述流体路径限定在所述A第一体积; 并且在所述限定与第二腔区域流体连接的第二体积，worin第二空腔区域的最大宽度的第三空腔区域（34）平面比第三腔区域的最大宽度，所述第二和第三空腔更大的 具有最大宽度做区域比第一腔区域的最大宽度大，并且worin至少所述第二体积的一部分被从所述流体路径中排除。

    Silicon processing method and silicon substrate with etching mask
    104.
    发明公开
    Silicon processing method and silicon substrate with etching mask 审中-公开
    Siliziumverarbeitungsverfahren und Siliziumsubstrat mitÄtzmaske

    公开(公告)号：EP2159191A2

    公开(公告)日：2010-03-03

    申请号：EP09168828.3

    申请日：2009-08-27

    Applicant: Canon Kabushiki Kaisha

    Inventor： Kato, Takahisa ,  Shimada, Yasuhiro

    IPC: B81C1/00

    CPC classification number: B81C1/00626 ,  B81B2201/0271 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0198

    Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.

    Abstract translation: 硅处理方法包括：在单晶硅衬底的主平面上形成掩模图案; 并对主表面进行结晶各向异性蚀刻，以形成包括（111）表面和与其等效的晶体表面的结构，并且具有宽度W1和长度L1。 主平面包括（100）表面和与其等效的（110）表面和与其等效的（110）表面和晶体表面。 在掩模图案中形成用于确定结构的宽度W1的确定部分。 掩模图案的宽度W1的确定部的宽度为宽度W2。 除了确定部分之外的掩模图案的宽度大于在掩模图案的长度方向上的宽度W2。

    Merged-mask micro-machining process
    105.
    发明公开
    Merged-mask micro-machining process 有权
    Mikromechanisches Herstellungsverfahren mitÜberblendetenMasken

    公开(公告)号：EP1510864A3

    公开(公告)日：2008-01-23

    申请号：EP04026039.0

    申请日：2000-07-13

    Applicant: ION Geophysical Corporation

    Inventor： Yu, Lianzhong ,  Ried, Robert P. ,  Goldberg, Howard D. ,  Yu, Duli

    IPC: G01P9/04 ,  G01P15/135 ,  G02B26/00 ,  C23F1/00 ,  G03F7/26 ,  G03F7/00

    CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

    Abstract: The present invention provides merged-mask processes for fabricating micromachined devices in general and mirrored assemblies for use in optical scanning devices in particular. A method of fabricating a three dimensional structure, comprising, providing a substrate, applying a layer of a first masking material onto the substrate, applying a layer of a second masking material onto the layer of the first masking material, patterning the layer of the second masking material, applying a layer of a third masking material onto the portions not covered by the patterned layer of the second masking material, the layer of the third masking material is at least as thick as the combined thickness of the layers of the first and second masking materials, patterning the layers of the first and third masking materials, etching the exposed portions of the substrate, etching the exposed portions of the layers of the first and third masking materials and etching the exposed portions of the substrate.

    Abstract translation: 本发明提供了用于一般地制造微机械装置和特别是用于光学扫描装置的镜面组件的合并掩模工艺。 一种制造三维结构的方法，包括：提供衬底，将第一掩蔽材料层施加到所述衬底上，将第二掩蔽材料层施加到所述第一掩模材料的所述层上，将所述第二掩模材料的所述层 掩模材料，将第三掩模材料层施加到未被第二掩模材料的图案化层覆盖的部分上，第三掩模材料的层至少与第一和第二掩模材料的层的组合厚度一样厚 掩模材料，图案化第一和第三掩模材料的层，蚀刻衬底的暴露部分，蚀刻第一和第三掩模材料的层的暴露部分并蚀刻衬底的暴露部分。

Patent Agency Ranking