公开(公告)号：EP2386521A2

公开(公告)日：2011-11-16

申请号：EP11161590.2

申请日：2011-04-08

Applicant: Omron Corporation

Inventor： Kasai, Takashi ,  Iida, Nobuyuki ,  Nakamura, Tomofumi

IPC: B81C1/00

CPC classification number: B81B7/0016 ,  B81B2201/0257 ,  B81B2207/012 ,  B81C2201/053 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/8592 ,  H01L2924/16151 ,  H04R19/005 ,  H04R31/00 ,  H01L2924/00014

Abstract: This invention aims to protect an outer peripheral part of an upper surface of a silicon substrate with a protective film using a back plate. A conductive diaphragm (33) is arranged on an upper side of a silicon substrate (32) including a back chamber (35), and the diaphragm (33) is supported with an anchor (37). An insulating plate portion (39) is fixed to an upper surface of the silicon substrate (32) so as to cover the diaphragm (33) with a gap. A conductive fixed electrode film (40) is arranged on a lower surface of the plate portion (39) to configure a back plate (34). The change in electrostatic capacitance between the fixed electrode film (40) and the diaphragm (33) is outputted to outside from a fixed side electrode pad (45) and a movable side electrode pad (46) as an electric signal. A protective film (53) is arranged in continuation to the plate portion (39) at an outer periphery of the plate portion (39), which protective film (53) covers the outer peripheral part of the upper surface of the silicon substrate (32) and the outer periphery of the protective film (53) coincides with the outer periphery of the upper surface of the silicon substrate (32).

公开(公告)号：EP2078694A2

公开(公告)日：2009-07-15

申请号：EP08105987.5

申请日：2008-12-16

Applicant: ROBERT BOSCH GMBH

Inventor： Teeffelen, Kathrin ,  Feyh, Ando ,  Leinenbach, Christina

IPC: B81C1/00

CPC classification number: B81C1/00896 ,  B81B2201/0257 ,  B81C2201/053

Abstract: Die Erfindung betrifft ein Schutzsystem für MEMS-Strukturen, mit einer fragilen offenen Struktur (12) und einer optionalen Opferschicht (13), aufgebracht auf einem Wafer (14), bei dem eine Schutzschicht (10) auf der Vorderseite der Struktur (12) aufgebracht ist, wobei die Schutzschicht (10) rückstandsfrei entfernbar ist, sowie ein Verfahren zur Vereinzelung von fragilen offenen MEMS-Strukturen.

Abstract translation: 系统具有脆弱的开放结构（12）和施加在晶片（14）上的可选牺牲层（13）。 保护层（10）附接在开放结构的前侧，其中脆性开放结构是膜。 在80至450摄氏度之间的温度下以无残留的方式除去保护层，并且由聚合物如聚降冰片烯和聚碳酸酯制成。 保护层通过辐射热分解，并通过离心涂覆聚合物施加。 还包括用于处理脆弱的开放微机电系统（MEMS）结构的方法的独立权利要求。

公开(公告)号：EP1119032B8

公开(公告)日：2008-03-19

申请号：EP01107622.1

申请日：1993-04-20

Applicant: Denso Corporation

Inventor： Fukada, Tsuyoshi ,  Yoshino, Yoshimi, c/o Intellectual Prop. Dept. ,  Tanizawa, Yukihiko, c/oIntellectual Prop. Dept.

IPC: H01L21/3063 ,  H01L21/78 ,  G01P15/12 ,  G01P15/08 ,  G01L9/00

CPC classification number: B81C1/00888 ,  B81B2201/0235 ,  B81C1/00158 ,  B81C2201/0114 ,  B81C2201/053 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

公开(公告)号：EP1108203B1

公开(公告)日：2005-03-16

申请号：EP99953629.5

申请日：1999-08-27

Applicant: Infineon Technologies AG

Inventor： AIGNER, Robert ,  HIEROLD, Christofer ,  KAPELS, Hergen ,  KOLB, Stefan ,  MAIER-SCHNEIDER, Dieter ,  OPPERMANN, Klaus-Günter ,  TIMME, Hans-Jörg ,  SCHEITER, Thomas ,  WERNER, Wolfgang

IPC: G01L9/00 ,  G01L9/12 ,  G01P15/08 ,  H04R7/10

CPC classification number: G01L9/0042 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00896 ,  B81C2201/053 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method for the production of a micromechanical component, comprising the production of a micromechanical component with sensor holes, wherein at least one component protective layer and/or spacer coating is applied on the component before separating the wafer into chips, wherein the component protective layer sealingly covers at least the walls of the holes extending parallel to the surface of the wafer and perpendicular to the surface of the wafer and the spacer coating sealingly covers at least the walls of the holes extending parallel to the surface of the wafer. The invention also relates to a micromechanical component produced according to the method disclosed in the invention and to the use of said components in microphones, pressure sensors or acceleration sensors.

公开(公告)号：EP1461287A2

公开(公告)日：2004-09-29

申请号：EP02795482.5

申请日：2002-07-17

Applicant: Rockwell Scientific Licensing, LLC

Inventor： DE NATALE, Jeffrey, F.

IPC: B81B3/00 ,  G02B26/08

CPC classification number: G02B6/3518 ,  B81B3/0083 ,  B81B2201/042 ,  B81C1/00214 ,  B81C2201/053 ,  G02B6/3584

Abstract: A new hybrid method of fabricating optical micro electro mechanical system (MEMS) devices is disclosed that uses both bulk and surface micromachining techniques, and a new optical MEMS device is also disclosed that is fabricated using the new method. The method includes the step of mounting a handle layer to one or more layers of MEMS structural material (12). Layers of structural and sacrificial material are then built up on the MEMS structural material using surface micromachining techniques (14). Drive electronics are mounted to the layers of structural and sacrificial material (17). The handle layer is removed (18) to reveal the MEMS structural layer and the sacrificial material within the various layers is dissolved (20). The new method is particularly applicable to fabricating optical MEMS devices, with the handle layer (54) being adjacent to a Si mirror layer (52). The surface micromachining layers form electrode (66) and spring structures (67, 68). Drive electronics (92) are then mounted on the layers of structural material, so that a bias can be applied to the MEMS structures. The handle layer (54) is removed from the mirror layer (52) to reveal the mirror's reflective surface, and the sacrificial material (64) is dissolved away, freeing the MEMS structures to operate. For optical or other MEMS arrays, a linking framework (70) can be included to attach the MEMS devices.

公开(公告)号：EP0683921B1

公开(公告)日：2004-06-16

申请号：EP94903348.4

申请日：1993-12-03

Applicant: CORNELL RESEARCH FOUNDATION, INC.

Inventor： SHAW, Kevin, A. ,  ZHANG, Z., Lisa ,  MACDONALD, Noel, C.

IPC: H01L21/44 ,  H01L21/449 ,  H01L21/302 ,  H01L23/48 ,  H01L29/06 ,  H01L29/86 ,  H01L29/84 ,  H01L29/96

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S73/01 ,  Y10S148/05

Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

公开(公告)号：EP1316993A1

公开(公告)日：2003-06-04

申请号：EP02258192.0

申请日：2002-11-28

Applicant: Denselight Semiconductors Pte Ltd.

Inventor： Cha Cher Liang, Randall ,  Nakamura, Hiroshi ,  Lam, Yee Loy ,  Teo, Kian Hin Victor

IPC: H01L21/308

CPC classification number: G02B6/3636 ,  B81B2203/033 ,  B81B2203/0384 ,  B81C1/00626 ,  B81C2201/053 ,  G02B6/3652 ,  G02B6/423

Abstract: A method for fabricating features of different depth in a semiconductor substrate by differential etching. Each of the features is first defined by a temporary mask and a metal layer is deposited and processed to provide a negative image of the original mask, the metal layer then acting as a protective layer during etching of the semiconductor substrate to fabricate the desired feature. The technique also allows the possibility that portions of two features of different depth may connect by opening into one another.

Abstract translation: 一种通过微分蚀刻在半导体衬底中制造不同深度的特征的方法。 每个特征首先由临时掩模限定，并且金属层被沉积​​和处理以提供原始掩模的负像，然后金属层在蚀刻半导体基板期间用作保护层以制造所需特征。 该技术还允许不同深度的两个特征的部分可以通过彼此打开而连接的可能性。

公开(公告)号：EP1119032A3

公开(公告)日：2001-10-17

申请号：EP01107622.1

申请日：1993-04-20

Applicant: Denso Corporation

Inventor： Fukada, Tsuyoshi ,  Yoshino, Yoshimi ,  Tanizawa, Yukihiko

IPC: H01L21/3063 ,  H01L21/78 ,  G01P15/12 ,  G01P15/08 ,  G01L9/00

CPC classification number: B81C1/00888 ,  B81B2201/0235 ,  B81C1/00158 ,  B81C2201/0114 ,  B81C2201/053 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

Abstract: There is disclosed a method and an apparatus for producing a semiconductor device having a diaphragm in the form of a thin part and an integrated circuit section with electrode on the same substrate, said method comprises a first step of forming a semiconductor layer of a second conduction type over a single-crystal semiconductor substrate of a first conduction type; a second step of forming the integrated circuit section with electrode on the semiconductor layer; a third step of forming the electrode in a scribe line area on the semiconductor layer and electrically connecting the electrode in the scribe line area to the electrode of the integrated circuit section; a fourth step of electrochemically etching predetermined parts of the substrate by transmitting electricity for the electrochemical etching through the electrode in the scribe line area, to form the diaphragm from the semiconductor layer and a fifth step of dicing the substrate into chips along the scribe line area, each of the chips forming the semiconductor device.

Abstract translation: 公开了一种用于制造半导体器件的方法和装置，该半导体器件具有薄膜形式的隔膜和在同一衬底上具有电极的集成电路部分，所述方法包括：形成第二导电半导体层的第一步骤 在第一导电类型的单晶半导体衬底上; 在半导体层上形成具有电极的集成电路部分的第二步骤; 在半导体层上的划线区域中形成电极并将划线区域中的电极与集成电路部分的电极电连接的第三步骤; 通过在划线区域中的电极传输用于电化学蚀刻的电力来电化学蚀刻基板的预定部分，从半导体层形成隔膜的第四步骤，以及沿着划线区域将基板切割成芯片的第五步骤 ，形成半导体器件的每个芯片。

公开(公告)号：EP0646246B1

公开(公告)日：1997-03-26

申请号：EP93911119.1

申请日：1993-05-06

Applicant: ANALOG DEVICES, INCORPORATED

Inventor： TSANG, Robert, W., K. ,  CORE, Theresa, A. ,  SHERMAN, Steven, J. ,  BROKAW, A., Paul

IPC: G01P15/08

CPC classification number: B81B3/001 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2201/112 ,  B81C2203/0742 ,  G01P15/0802 ,  G01P15/125 ,  G01P15/131 ,  G01P2015/0814

Abstract: The invention comprises a method for fabricating a monolithic chip containing integrated circuitry as well as a suspended polysilicon microstructure. The inventive method comprises 67 processes which are further broken down into approximately 330 steps. The processes and their arrangement allow for compatible fabrication of transistor circuitry and the suspended polysilicon microstructure on the same chip.

公开(公告)号：EP0427930A2

公开(公告)日：1991-05-22

申请号：EP90116543.1

申请日：1990-08-29

Applicant: International Business Machines Corporation

Inventor： Bassous, Ernest ,  Blum, Joseph M. ,  Chan, Kevin K. ,  Lamberti, Angela C.

IPC: G03F1/14

CPC classification number: B81C1/00158 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/053 ,  B81C2203/019 ,  G01L9/0042 ,  G03F1/22 ,  Y10S438/977

Abstract: The method of fabrication of a monolithic silicon membrane structure in which the membrane and its supporting framework are constructed from a single ultra thick body of silicon. The fabrication sequence includes the steps of providing a doped membrane layer on the silicon body, forming an apertured mask on the silicon body, and removal of an unwanted silicon region by mechanical grinding and chemical etching to provide a well opening in the silicon body terminating in the doped membrane.

Abstract translation: 制造单片硅膜结构的方法，其中膜及其支撑框架由单个超厚体硅构成。 制造顺序包括以下步骤：在硅体上提供掺杂的膜层，在硅体上形成孔径掩模，并通过机械研磨和化学蚀刻去除不想要的硅区域，以在硅体中终止孔 掺杂膜。