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公开(公告)号：GB2284942B
公开(公告)日：1997-06-18
申请号：GB9425244
申请日：1994-12-14
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： SUNG HEE KYUNG , LEE CHANG HWA , KIM TAE HONG , LEE SANG SEOK , CHOI TAE GOO
Abstract: A dielectric resonator includes a dielectric block having an open surface at one of the surfaces thereof, the remaining surfaces being plated with a conductor. The dielectric block has an inner conductor hole formed at a surface of the dielectric block opposite to the open surface, the inner conductor hole extending a predetermined depth toward the open surface such that it does not perforate through the open surface. An electrode pattern is formed on the open surface such that it faces an end surface of the inner conductor hole, the electrode pattern being adapted to provide an input/output capacitor. The dielectric block has a coupling window formed on a predetermined portion of one of the surfaces of the dielectric block, except for the open surface and the surface formed with the inner conductor hole, at a position adjacent to one of the open surface and the surface formed with the inner conductor hole. The coupling window is free of the plated conductor and adapted to control a coupling degree of the resonator to another resonator. Other embodiments include integral type filters having resonators in a single dielectric block.
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公开(公告)号：GB2306716A
公开(公告)日：1997-05-07
申请号：GB9622841
申请日：1996-11-01
Applicant: KOREA TELECOMMUNICATION
Inventor： KIM KYEOUN SOO , JANG SOON HWA , KWON SOON HONG
Abstract: A circuit for performing a bit-serial matrix transposition operation comprises an input shift register module 11 for inputting matrix elements of length k bits. The input shift register module 11 outputs the data in units of k/N bits and applies the units to a bit-serial transposition module 12. An output multiplexer module 13 selects k/N-bit data units from the bit-serial transposition module 12 in response to a switching control signal. An output register module 14 receives the data output from the output multiplexer module 13 in the k/N bit units and outputs N data in units of k bits which make up the transposed matrix.
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公开(公告)号：FR2738438A1
公开(公告)日：1997-03-07
申请号：FR9613644
申请日：1996-11-08
Applicant: KOREA TELECOMMUNICATION
Inventor： PARK ILL HWAN , JANG CHUNG RYONG
Abstract: An identification scheme which allows a prover to identify his own identity to a verifier more certainly and prevents already used authentication information from being re-used, a key exchange which uses a common secret key between two users in order not to allow an unauthorized to find it out, a digital signature scheme giving message recovery and digital signature scheme with appendix for producing a digital signature of a message recovery type or appendix type according to the size of a message to be signed, a multi-digital signature scheme for allowing multiple signers to generate digital signatures with respect to the same message and producing them in a message recovery type or appendix type according to the length of the message to be signed, and a blind digital signature scheme for producing a digital signature when a message to be signed should not be opened to the public as well as the signer and therefore a signer does not know the contents thereof.
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公开(公告)号：GB9622841D0
公开(公告)日：1997-01-08
申请号：GB9622841
申请日：1996-11-01
Applicant: KOREA TELECOMMUNICATION
Abstract: A very large scale integrated circuit for performing a bit-serial matrix transposition operation, comprising an input shift register module for inputting N multiplied results of two NxN matrixes in the unit of k bits and outputting them in the unit of k/N bits in response to a load signal, a bit-serial transposition module for selecting k/N-bit data from the input shift register module in response to a switching control signal, an output multiplexer module for selecting k/N-bit data from the bit-serial transposition module in response to the switching control signal, and an output register module for inputting output data from the output multiplexer module in the unit of k/N bits and outputting N data in the unit of k bits. According to the present invention, when an NxN matrix transposition operation is performed, the operation occupancy of transposition cells becomes 100% after an N-input delay occurs. Also, the processing unit of data becomes smaller by using a bit-serial processing algorithm. Therefore, the high-speed operation can be performed. Further, the number of gates can be reduced in the integrated circuit. Moreover, because the integrated circuit has a pipelined structure, it is applicable to a multi-dimensional signal processing system requiring a high-speed processing operation.
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公开(公告)号：FR2735308A1
公开(公告)日：1996-12-13
申请号：FR9606154
申请日：1996-05-17
Applicant: KOREA TELECOMMUNICATION
Inventor： AHN KEUM HYUG , LEE YUN HO , PARK ILL HWAN , JANG CHUNG RYONG
Abstract: The method involves the sender (A) selecting a first arbitrary number (r1) and calculating a remainder x from a preset formula to produce an identification number h(x,IDA) which is transmitted to the receiver (B). The sender also selects second and third random numbers (r2,r3) and calculates further remainders (r4,r5) using predetermined formulae. A further calculation is then carried out using the initially generated identification and the new remainders to provide further remainders (y1,y2). The coding produced is passed to the receiver. The receiver can then validate and recover the message received, using further agreed formulae.
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Patent Agency Ranking
公开(公告)号：DE4445344C2
公开(公告)日：1996-10-02
申请号：DE4445344
申请日：1994-12-19
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： RYUM BYUNG-RYUL , HAN TAE-HYEON , LEE SOO-MIN , CHO DEOK-HO , LEE SEONG-HEARN , KANG JIN-YOUNG
IPC: H01L21/331 , H01L21/762 , H01L21/76 , H01L29/73 , H01L27/12 , H01L21/20 , H01L21/84
Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.
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公开(公告)号：GR1002157B
公开(公告)日：1996-02-22
申请号：GR92100488
申请日：1992-11-05
Applicant: KOREA TELECOMMUNICATION
Inventor： YONG KYU PARK , CHONG RAK LEE
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公开(公告)号：FR2718309A1
公开(公告)日：1995-10-06
申请号：FR9503802
申请日：1995-03-31
Applicant: KOREA TELECOMMUNICATION
Inventor： AHN KEUM HYUG , JANG CHUNG RYONG , PARK ILL HWAN
Abstract: The method involves establishing system parameters p and g where g lies between 1 and q and has a value of 1 when it is raised to the qth power and then divided by p. The coefficient for q can be replaced by p-1. A number n of secret and public keys are used for each user where n is not less than 2. The public keys Vn correspond respectively to the secret keys Sn and numbers between 1 and q are produced based on the equation Vn=(g Sn)mod p.
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公开(公告)号：GB2261092B
公开(公告)日：1995-06-14
申请号：GB9213381
申请日：1992-06-24
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.
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