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    Built-in test circuit and method for an integrated circuit
    111.
    发明公开
    Built-in test circuit and method for an integrated circuit 审中-公开
    Eingebaute Testschaltung und -verfahren在einer integrierten Schaltung

    公开(公告)号：EP1231608A1

    公开(公告)日：2002-08-14

    申请号：EP01301092.1

    申请日：2001-02-07

    Applicant: STMicroelectronics Limited

    Inventor： Firth, Steven ,  Barnes, William

    IPC: G11C29/00

    CPC classification number: G11C29/14 ,  G11C29/48

    Abstract: Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to the integrated circuit; input selection means operable to control which of the test data and the input data are received at the integrated circuit; capture circuitry for capturing output data from the integrated circuit and generating response data; output selection means operable to select which of the output data and the response data are received by the response scan cells.

    Abstract translation: 用于测试集成电路的测试电路，所述集成电路可配置为接受来自激励扫描单元的输入数据，并向响应扫描单元提供输出数据，所述测试电路包括用于向所述集成电路提供测试数据的激励电路; 输入选择装置，用于控制在集成电路处接收的测试数据和输入数据中的哪一个; 用于从集成电路捕获输出数据并产生响应数据的捕获电路; 输出选择装置，用于选择响应扫描单元接收哪一个输出数据和响应数据。

    Solid state imaging device
    114.
    发明公开
    Solid state imaging device 审中-公开
    Festkörperbildaufnahmevorrichtung

    公开(公告)号：EP1207686A1

    公开(公告)日：2002-05-22

    申请号：EP01300101.1

    申请日：2001-01-05

    Applicant: STMicroelectronics Limited

    Inventor： Raynor, Jeffrey ,  Denyer, Peter ,  Hurwitz, Jonathan

    IPC: H04N3/15

    CPC classification number: H04N5/37452 ,  H04N5/353 ,  H04N5/3575 ,  H04N5/378

    Abstract: An image plane consists of a number of pixels, two of which are shown. Each pixel comprises a photodiode and two transistors (M1, M2). Each pixel is connected by a signal bus (10) to a respective storage node located off the image plane. Each storage node comprises two capacitors (Csn_1, Csn_2) and associated switches (S2_1, S2_2). The transistor M2 applies a reset pulse to the pixel, and the transistor M1 connects the pixel to a given conductor of the signal bus (10) and thence to the storage node. The pixel transistors can be operated simultaneously, and the sensed values subsequently transferred from the storage nodes sequentially.

    Abstract translation: 图像平面由多个像素组成，其中两个显示。 每个像素包括光电二极管和两个晶体管（M1，M2）。 每个像素通过信号总线（10）连接到位于图像平面外的各个存储节点。 每个存储节点包括两个电容器（Csn_1，Csn_2）和相关联的开关（S2_1，S2_2）。 晶体管M2向像素施加复位脉冲，晶体管M1将像素连接到信号总线（10）的给定导体，然后连接到存储节点。 像素晶体管可以同时操作，并且随后从存储节点顺序传送感测值。

    Circuitry for reading from and writing to memory cells
    115.
    发明公开
    Circuitry for reading from and writing to memory cells 审中-公开
    Schaltungen zum Lesen Schreiben von Speicherzellen

    公开(公告)号：EP1162624A2

    公开(公告)日：2001-12-12

    申请号：EP01304380.7

    申请日：2001-05-17

    Applicant: STMicroelectronics Limited

    Inventor： Docker, Steven Charles ,  Galbi, Duane

    IPC: G11C7/10

    CPC classification number: G11C7/1069 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078

    Abstract: Circuitry for reading from and writing to memory cells of a group of memory cells. The circuitry comprises read circuitry and write circuitry each connectable to bit lines associated with respective ones of the memory cells. The read circuitry is arranged to read from the cells and the write circuitry is arranged to write to the cells. Wherein the read circuitry and write circuitry are configured so that more cells in the group can be simultaneously written to during a write operation than can be simultaneously read from during a read operation.

    Abstract translation: 用于从一组存储器单元读取和写入存储单元的电路。 电路包括读取电路和写入电路，每个可读取电路和写入电路可连接到与相应存储器单元相关联的位线。 读取电路被布置成从单元读取并且写入电路被布置成写入单元。 其中读取电路和写入电路被配置为使得在写入操作期间可以在读取操作期间同时读取组中的更多单元。

    Debugging device and method
    116.
    发明公开
    Debugging device and method 审中-公开
    Vorrichtung und Verfahren zur Fehlerbeseitigung

    公开(公告)号：EP1148420A1

    公开(公告)日：2001-10-24

    申请号：EP01300902.2

    申请日：2001-02-01

    Applicant: STMicroelectronics Limited

    Inventor： Phillips, Mark

    IPC: G06F11/36

    CPC classification number: G06F11/3656

    Abstract: During debugging of target system by a host system, s single stack is used for an exception by a set of applications running on the processor of the target. To achieve this, the stack is dynamically loaded by the host to a reserved memory region, and a vector of the target is set to point to that reserved region. The exception handlers of each application then use the vector to access the stack.

    Abstract translation: 在主机系统对目标系统的调试期间，单个堆栈用于在目标处理器上运行的一组应用程序的异常。 为了实现这一点，堆栈被主机动态加载到保留的存储器区域，并且目标的向量被设置为指向该保留区域。 每个应用程序的异常处理程序然后使用向量访问堆栈。

    A method of converting data
    119.
    发明公开
    A method of converting data 审中-公开
    Ein Verfahren zur Datenumsetzung

    公开(公告)号：EP1096397A1

    公开(公告)日：2001-05-02

    申请号：EP00309153.5

    申请日：2000-10-17

    Applicant: STMicroelectronics Limited

    Inventor： Ballam, Peter

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G06F17/5036

    Abstract: A method is described for converting a data set for use with a digital model of a hardware cell into an expanded data set for use with an analogue model of the hardware cell. The method comprises the steps of determining the signal required to drive one or more pins of said analogue model by analysing whether the signals used in said digital model are in a first category or a second category, said first category containing relatively simple signals and said second category containing relatively complex signals, and providing the signal required for the one or more pins in the analogue model in dependence on said analysis.

    Abstract translation: 描述了一种用于将用于硬件单元的数字模型的数据集转换成与硬件单元的模拟模型一起使用的扩展数据集的方法。 该方法包括以下步骤：通过分析在所述数字模型中使用的信号是否处于第一类别或第二类别来确定驱动所述模拟模型的一个或多个引脚所需的信号，所述第一类别包含相对简单的信号，并且所述第二类别 类别包含相对复杂的信号，并且根据所述分析提供模拟模型中的一个或多个引脚所需的信号。

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