公开(公告)号：KR1020040105456A

公开(公告)日：2004-12-16

申请号：KR1020030036834

申请日：2003-06-09

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  남갑진 ,  김영선 ,  권종완 ,  김기철 ,  최한메

IPC: H01L21/20

Abstract: PURPOSE: A method for forming a capacitor dielectric layer is provided to restrict generation of leakage current by forming a complex dielectric layer with a dielectric having an excellent leakage characteristic and a dielectric layer having a large dielectric constant. CONSTITUTION: A first reaction material is chemically absorbed into a substrate by supplying a first reaction gas(51). The first reaction gas is purged(52). A second reaction material is chemically absorbed into the substrate by supplying a second reaction gas(53). The second reaction gas is purged(54). The first and the second reaction materials are oxidized by supplying an oxidizer. A complex oxide of first and second oxides is formed by oxidizing the first and the second reaction materials(55).

Abstract translation: 目的：提供一种用于形成电容器电介质层的方法，通过形成具有优异漏电特性的电介质和具有大介电常数的电介质层的复电介质层来限制漏电流的产生。 构成：通过提供第一反应气体（51）将第一反应材料化学吸收到基底中。 第一反应气体被吹扫（52）。 通过供应第二反应气体（53）将第二反应材料化学吸收到基底中。 第二反应气体被清除（54）。 第一和第二反应物质通过供给氧化剂被氧化。 通过氧化第一和第二反应材料（55）形成第一和第二氧化物的复合氧化物。

公开(公告)号：KR1020040088172A

公开(公告)日：2004-10-16

申请号：KR1020030022285

申请日：2003-04-09

Applicant: 삼성전자주식회사

Inventor： 남갑진 ,  김성태 ,  김영선 ,  권종완 ,  김기철 ,  임재순

IPC: H01L21/8242

Abstract: PURPOSE: A method for forming a semiconductor device with a capacitor is provided to prevent degradation of a dielectric film by performing diffusion plasma annealing after depositing the dielectric film. CONSTITUTION: A lower electrode(112a) is formed on a semiconductor substrate(101). A pretreatment layer(114) is formed on the lower electrode by using a rapid thermal nitridation method, a rapid thermal oxidation method or chemical vapor deposition method. A dielectric film is deposited on the resultant structure. By performing diffusion plasma annealing, an annealed dielectric film(116a) is formed.

Abstract translation: 目的：提供一种用于形成具有电容器的半导体器件的方法，以通过在沉积电介质膜之后进行扩散等离子体退火来防止电介质膜的劣化。 构成：在半导体衬底（101）上形成下电极（112a）。 通过使用快速热氮化法，快速热氧化法或化学气相沉积法在下电极上形成预处理层（114）。 在所得结构上沉积介电膜。 通过进行扩散等离子体退火，形成退火的电介质膜（116a）。

公开(公告)号：KR1020040076447A

公开(公告)日：2004-09-01

申请号：KR1020030011794

申请日：2003-02-25

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  김성태 ,  김영선 ,  황기현 ,  남갑진 ,  김기철 ,  이주원 ,  박재영

IPC: H01L27/108

CPC classification number: H01L28/57 ,  H01L21/3141 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/65

Abstract: PURPOSE: A method for forming a capacitor of a semiconductor device is provided to reduce the thermal damage of the capacitor and a contact resistor by forming the capacitor under the low temperature of 600 degrees centigrade. CONSTITUTION: The first conductive layer(12) is formed on an upper surface of a substrate(10). An anti-reaction layer(14) for preventing the oxidation of the first conductive layer is formed on an upper surface of the first conductive layer under predetermined temperature conditions in order to prevent a phase transition phenomenon. A dielectric layer(16) is formed on a surface of the anti-reaction layer. The second conductive layer(18) is formed on a surface of the dielectric layer.

Abstract translation: 目的：提供一种用于形成半导体器件的电容器的方法，通过在600摄氏度的低温下形成电容器来减少电容器和接触电阻器的热损伤。 构成：第一导电层（12）形成在基板（10）的上表面上。 为了防止相变现象，在第一导电层的上表面上，在规定的温度条件下，形成防止第一导电层氧化的防反应层（14）。 在抗反应层的表面上形成介电层（16）。 第二导电层（18）形成在电介质层的表面上。

公开(公告)号：KR1020030097442A

公开(公告)日：2003-12-31

申请号：KR1020020034815

申请日：2002-06-21

Applicant: 삼성전자주식회사

Inventor： 김성태 ,  김영선 ,  남갑진 ,  김기철 ,  임재순

IPC: H01L21/318

Abstract: PURPOSE: A method for fabricating a nitride layer of a semiconductor device is provided to reduce plasma damage to a material layer under the nitride layer by forming pre-activated nitrogen gas and by inducing the nitrogen gas to a nitridification chamber so that the nitrogen gas is activated to be a plasma state. CONSTITUTION: The material layer is formed on a semiconductor substrate. The semiconductor substrate with the material layer is induced to the nitridification chamber(S150). Nitrogen gas is induced to a pre-activation unit connected to the nitridification chamber to form pre-activated nitrogen gas(S155). The pre-activated nitrogen gas is induced to the nitridification chamber to form activated nitrogen gas(S160). The activated nitrogen gas reacts with the material layer to form a nitride layer on the material layer(S165).

Abstract translation: 目的：提供一种制造半导体器件的氮化物层的方法，通过形成预活化的氮气并通过将氮气引入氮化室来减少对氮化物层下面的材料层的等离子体损伤，使氮气为 激活成等离子体状态。 构成：材料层形成在半导体衬底上。 将具有材料层的半导体衬底引入氮化室（S150）。 氮气被诱导到与氮化室连接的预激活单元以形成预活化的氮气（S155）。 将预活化的氮气引入硝化室以形成活性氮气（S160）。 活性氮气与材料层反应，在材料层上形成氮化物层（S165）。

公开(公告)号：KR1020020013276A

公开(公告)日：2002-02-20

申请号：KR1020000046936

申请日：2000-08-14

Applicant: 삼성전자주식회사

Inventor： 남갑진 ,  원석준

IPC: H01L27/108

Abstract: PURPOSE: A method for forming a capacitor of a semiconductor device having an upper electrode including a noble metal layer is provided to make a barrier metal layer and a polysilicon layer absorb residual thermal stress generated on the noble metal layer in a heat treatment process, by forming a tri layer composed of the noble metal layer, the barrier metal layer and the polysilicon layer as an upper electrode of a dielectric layer. CONSTITUTION: A lower electrode(103) connected to a predetermined active region of a semiconductor substrate(100) is formed on the substrate. The dielectric layer(104) is formed on the lower electrode. The noble metal layer(105) is formed on the dielectric layer. A conductive barrier metal layer(106) and the polysilicon layer(107) are sequentially formed on the noble metal layer. The upper electrode composed of the noble metal layer, the barrier metal layer and the polysilicon layer is formed.

Abstract translation: 目的：提供一种形成具有包括贵金属层的上电极的半导体器件的电容器的方法，以使得阻挡金属层和多晶硅层在热处理过程中吸收在贵金属层上产生的残余热应力，由 形成由贵金属层，阻挡金属层和多晶硅层构成的三层作为电介质层的上电极。 构成：在基板上形成连接到半导体基板（100）的预定有源区的下电极（103）。 电介质层（104）形成在下电极上。 贵金属层（105）形成在电介质层上。 导电阻挡金属层（106）和多晶硅层（107）依次形成在贵金属层上。 形成由贵金属层，阻挡金属层和多晶硅层构成的上部电极。

公开(公告)号：KR1020020005827A

公开(公告)日：2002-01-18

申请号：KR1020000039267

申请日：2000-07-10

Applicant: 삼성전자주식회사

Inventor： 남갑진 ,  김영선

IPC: H01L21/8242

Abstract: PURPOSE: A method for fabricating a cylinder type capacitor of a semiconductor device is provided to improve a cell capacitance of a semiconductor device by forming a capacitor having a three-dimensional cylindrical structure. CONSTITUTION: The first insulating layer(104) and an etch stop layer are deposited on a semiconductor substrate(100). A contact plug(110) is formed by patterning the first insulating layer(104) and the etch stop layer. A pattern of the second insulating(112) pattern of a concave shape is formed on the semiconductor substrate(100) in order to form a capacitor. The first lower electrode layer(114) is formed on the semiconductor substrate(110) by using blanket method. A spacer is formed within a groove of the concave shape. The second lower electrode layer(118) is formed on the semiconductor substrate(100). The third insulating layer is deposited on the semiconductor substrate(100). The second insulating layer is exposed by polishing the semiconductor substrate(100). A lower electrode layer having three pillars is formed by etching the semiconductor substrate(100). A dielectric layer and an upper electrode layer are formed on the lower electrode layer.

Abstract translation: 目的：提供一种用于制造半导体器件的圆柱型电容器的方法，以通过形成具有三维圆柱形结构的电容器来改善半导体器件的单元电容。 构成：第一绝缘层（104）和蚀刻停止层沉积在半导体衬底（100）上。 通过图案化第一绝缘层（104）和蚀刻停止层来形成接触插塞（110）。 为了形成电容器，在半导体衬底（100）上形成凹形的第二绝缘（112）图案的图形。 第一下电极层（114）通过使用覆盖法形成在半导体衬底（110）上。 间隔件形成在凹形槽的凹槽内。 第二下电极层（118）形成在半导体衬底（100）上。 第三绝缘层沉积在半导体衬底（100）上。 通过研磨半导体衬底（100）来暴露第二绝缘层。 通过蚀刻半导体衬底（100）形成具有三个柱的下电极层。 电介质层和上电极层形成在下电极层上。

公开(公告)号：KR100304699B1

公开(公告)日：2001-09-26

申请号：KR1019990000055

申请日：1999-01-05

Applicant: 삼성전자주식회사

Inventor： 남갑진 ,  원석준 ,  박기연 ,  형용우 ,  박영욱

IPC: H01L27/108

CPC classification number: H01L21/02183 ,  C03C23/0075 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/31604 ,  H01L27/1085 ,  H01L28/56

Abstract: 탄탈륨산화막으로이루어지는유전막을갖춘커패시터제조방법에관하여개시한다. 본발명에서는반도체기판의활성영역에전기적으로연결되는하부전극을형성한다. 상기하부전극의표면에실리콘산화물, 실리콘질화물및 이들의조합으로이루어지는군에서선택되는성분을포함하는전처리막을형성한다. Ta 전구체를사용하여소정의온도범위에서선택되는제1 온도에서증착된제1 유전막과, 상기소정의온도범위에서선택되고상기제1 온도와는다른제2 온도에서증착된제2 유전막으로이루어지는유전막을상기전처리막위에형성한다. 상기유전막을산소분위기에서열처리하는단계를포함한다.

公开(公告)号：KR1020010037025A

公开(公告)日：2001-05-07

申请号：KR1019990044303

申请日：1999-10-13

Applicant: 삼성전자주식회사

Inventor： 형용우 ,  박영욱 ,  남갑진

IPC: H01L27/108

Abstract: PURPOSE: A method for manufacturing a capacitor storage electrode having an uneven surface of a semiconductor device is to provide the storage electrode suitable for a highly integrated semiconductor capacitor, by maximizing an effective area of the capacitor storage electrode and minimizing the thickness of the storage electrode, and by minimizing an area occupied by the storage electrode in a cell. CONSTITUTION: An insulating layer having a contact hole exposing a predetermined region of a substrate(21) is formed. The contact hole is buried with a conductive material and planarized to form a contact plug(25). The contact plug is exposed to the surface of the insulating layer, and a molding layer has an uneven surface and a storage electrode supporting part(30) in which a storage electrode(32) is to be located. A conductive material is deposited on the entire surface including the molding layer to form the storage electrode. The storage electrode layer deposited on an upper surface of the molding layer is eliminated, and the molding layer is exposed to leave a space between electrodes. The exposed molding layer is eliminated to form an uneven storage electrode.

Abstract translation: 目的：制造具有半导体器件不平坦表面的电容器存储电极的方法是通过最大化电容器存储电极的有效面积并使存储电极的厚度最小化来提供适合于高度集成的半导体电容器的存储电极 并且通过使小室中的存储电极占据的面积最小化。 构成：形成具有暴露基板（21）的预定区域的接触孔的绝缘层。 接触孔用导电材料掩埋并平坦化以形成接触塞（25）。 接触插塞暴露于绝缘层的表面，成型层具有不平坦表面和存放电极（32）的存储电极支撑部（30）。 在包括成型层的整个表面上沉积导电材料以形成存储电极。 消除了沉积在成型层的上表面上的存储电极层，并且模塑层被暴露以在电极之间留下空间。 消除暴露的成型层以形成不均匀的存储电极。

公开(公告)号：KR1020000050306A

公开(公告)日：2000-08-05

申请号：KR1019990000055

申请日：1999-01-05

Applicant: 삼성전자주식회사

Inventor： 남갑진 ,  원석준 ,  박기연 ,  형용우 ,  박영욱

IPC: H01L27/108

CPC classification number: H01L21/02183 ,  C03C23/0075 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/31604 ,  H01L27/1085 ,  H01L28/56

Abstract: PURPOSE: A method for manufacturing a capacitor having a tantalum oxidation layer is provided to increase productivity, by improving an electrical characteristic of the capacitor, and by reducing an incubation time in an evaporation process for forming the tantalum oxidation layer. CONSTITUTION: A method for manufacturing a capacitor having a tantalum oxidation layer comprises four steps. The first step is to form a lower electrode electrically connected to an active region of a semiconductor substrate. The second step is to form a prior treatment layer including a component selected from a group of a silicon oxidation material, a silicon nitride material and a composition of the two, on the surface of the lower electrode. The third step is to form a dielectric layer on the prior treatment layer, in which the dielectric layer is composed of a first dielectric layer and a second dielectric layer. The first dielectric layer is evaporated in a first temperature selected from a predetermined scope of temperature. The second dielectric layer is evaporated in a second temperature different from the first temperature, the second temperature being selected from the predetermined scope of temperature. The fourth step is to perform a heat treatment regarding the dielectric layer in an oxygen atmosphere.

Abstract translation: 目的：提供一种用于制造具有钽氧化层的电容器的方法，以通过改善电容器的电特性以及通过减少用于形成钽氧化层的蒸发过程中的孵育时间来提高生产率。 构成：制造具有钽氧化层的电容器的方法包括四个步骤。 第一步是形成电连接到半导体衬底的有源区的下电极。 第二步是在下电极的表面上形成包括选自硅氧化材料，氮化硅材料和二者的组成的组分的预处理层。 第三步骤是在现有处理层上形成电介质层，其中电介质层由第一介电层和第二电介质层构成。 第一介电层在选自预定温度范围的第一温度下蒸发。 第二介电层在与第一温度不同的第二温度下蒸发，第二温度选自预定的温度范围。 第四步是在氧气氛中对电介质层进行热处理。

公开(公告)号：KR1020000007802A

公开(公告)日：2000-02-07

申请号：KR1019980027317

申请日：1998-07-07

Applicant: 삼성전자주식회사

Inventor： 남갑진 ,  남상돈 ,  원석준 ,  형용우

IPC: H01L27/04

Abstract: PURPOSE: A capacitor and fabrication method thereof are provided to prevent a generation of void and improve a leakage current of dielectric layer by using multi-dielectric layers having an amorphous layer between therein. CONSTITUTION: The capacitor structure comprises a semiconductor substrate(40); a lower electrode(46) formed on the semiconductor substrate(40); a diffusion barrier layer(48) on the lower electrode; multi-dielectric layers(50a, 54a) having an amorphous layer(52) formed at interface between the multi-dielectric layers; and an upper electrode(58) formed on the multi-dielectric layers. The amorphous layer(52) made of substance having a high crystallization temperature compared to the dielectric layers(50a, 54a).

Abstract translation: 目的：提供电容器及其制造方法，以通过使用其间具有非晶层的多电介质层来防止空隙的产生和电介质层的漏电流。 构成：电容器结构包括半导体衬底（40）; 形成在所述半导体衬底（40）上的下电极（46）; 在下电极上的扩散阻挡层（48）; 具有形成在所述多电介质层之间的界面处的非晶层（52）的多电介质层（50a，54a） 和形成在多电介质层上的上电极（58）。 与介电层（50a，54a）相比，具有高结晶温度的物质制成的非晶层（52）。